A 6.0–13.5 GHz Alias-Locked Loop Frequency Synthesizer in 130 nm CMOS

A 6.0-13.5 GHz alias-locked loop (ALL) frequency synthesizer is designed and simulated in 130 nm CMOS. Using an aliasing divider, the ALL architecture makes it possible to create high-speed frequency synthesis circuits without relying on a traditional divider clocked at fVCO in the feedback path. In this implementation, a new architecture of high frequency ring oscillator is proposed with a feedforward path and selectable modes of operation for different frequency ranges. This ring oscillator provides both a high oscillating frequency and a wide tuning range. Simulation results have shown that the design synthesizes the desired frequencies and consumes 30.01 mW @ 13.0 GHz with a 1.2 V power supply.

[1]  Duncan G. Elliott,et al.  An alias-locked loop frequency synthesis architecture , 2008, 2008 IEEE International Symposium on Circuits and Systems.

[2]  Eric A. M. Klumperink,et al.  Spur-reduction techniques for PLLs using sub-sampling phase detection , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[3]  Lee-Sup Kim,et al.  A 200 MHz 13 mm/sup 2/ 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme , 1994 .

[4]  Wang Ling Goh,et al.  1.8-V 10-GHZ ring VCO design using 0.18-μm CMOS technology , 2005, Proceedings 2005 IEEE International SOC Conference.

[5]  Orla Feely,et al.  Nonlinear dynamics of alias-locked loop , 2009, 2009 European Conference on Circuit Theory and Design.

[6]  Minoru Fujishima,et al.  32.8 70GHz CMOS Harmonic Injection-Locked Divider , 2006 .

[7]  Chih-Ming Hung,et al.  A 410GHz CMOS Push-Push Oscillator with an On-Chip Patch Antenna , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[8]  Mohamed I. Elmasry,et al.  A low power monolithic subsampled phase-locked loop architecture for wireless transceivers , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[9]  Eric A. M. Klumperink,et al.  A 2.2GHz 7.6mW sub-sampling PLL with −126dBc/Hz in-band phase noise and 0.15psrms jitter in 0.18µm CMOS , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[10]  W. Rhee,et al.  Design of high-performance CMOS charge pumps in phase-locked loops , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[11]  Y. A. Eken,et al.  A 5.9-GHz voltage-controlled ring oscillator in 0.18-/spl mu/m CMOS , 2004, IEEE Journal of Solid-State Circuits.

[12]  Liang-Hung Lu,et al.  40GHz Wide-Locking-Range Regenerative Frequency Divider and Low-Phase-Noise Balanced VCO in 0.18μm CMOS , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[13]  V.G. Oklobdzija,et al.  Improved sense-amplifier-based flip-flop: design and measurements , 2000, IEEE Journal of Solid-State Circuits.

[14]  M. Horowitz,et al.  Precise delay generation using coupled oscillators , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[15]  M. Fujishima,et al.  70GHz CMOS Harmonic Injection-Locked Divider , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.