On-chip contrastive divergence learning in analogue VLSI

We have mapped the contrastive divergence learning scheme of the product of experts (PoE) onto electrical circuits. The issues raised during that hardware translation are discussed in This work and some circuits presenting our solutions are described. The entire learning rule is implemented in mixed-signal VLSI on a 0.6 /spl mu/m CMOS process. Chips results validating our approach and methodology are also presented.

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