A high power-efficient LVDS output driver with adjustable feed-forward capacitor compensation

This paper presents a high power-efficient low voltage differential signaling (LVDS) output driver with adjustable feed-forward capacitor compensation. Compared to conventional LVDS output driver, the proposed output driver helps to significantly reduce the requirement of driving capability of pre-driver by increasing the rising and falling time of outputs. In addition, its output swing is adjustable based on different loadings. The proposed LVDS output driver consumes 3.04mW with a transmission data rate of 6Gb/s, achieving a power efficiency of 0.51mW/Gb/s. This output driver circuit is implemented in a 65 nm CMOS process with a core area of 0.025mm2.

[1]  A. Tajalli,et al.  A Slew Controlled LVDS Output Driver Circuit in 0.18 $\mu$m CMOS Technology , 2009, IEEE Journal of Solid-State Circuits.

[2]  Yue Lu,et al.  Design and Analysis of Energy-Efficient Reconfigurable Pre-Emphasis Voltage-Mode Transmitters , 2013, IEEE Journal of Solid-State Circuits.

[3]  Tawee Tanbun-Ek,et al.  A systems perspective on digital interconnection technology , 1992 .

[4]  P. M. Chau,et al.  A 622 MHz stand-alone LVDS driver pad in 0.18-/spl mu/m CMOS , 2001, Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257).

[5]  A. Boni,et al.  LVDS I/O interface for Gb/s-per-pin operation in 0.35-/spl mu/m CMOS , 2001 .

[6]  G. G. Stokes.  "J." , 1890, The New Yale Book of Quotations.

[7]  J. Choma,et al.  Architecture and Implementation of a Low-Power LVDS Output Buffer for High-Speed Applications , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[8]  Young-Hyun Jun,et al.  A 6-Gbps/pin Half-Duplex LVDS I/O for High-Speed Mobile DRAM , 2005, 2005 IEEE Asian Solid-State Circuits Conference.