System level performance analysis of carbon nanotube global interconnects for emerging chip multiprocessors

Although carbon nanotubes (CNTs) have been widely proposed as interconnect fabrics for future ultra deep submicron (UDSM) technologies, there is a lack of system-level performance analysis using these interconnects. In this paper, we investigate the performance of four CNT alternatives that may replace conventional copper (Cu) interconnects at the global interconnect level - (i) single walled CNTs (SWCNTs), (ii) SWCNT bundles, (Hi) multi-walled CNTs (MWCNTs) and (iv) bundles of mixed SWCNTs/MWCNTs. Detailed RLC equivalent circuit models for conventional CNT interconnects are described and used to calculate propagation delays. These models are then incorporated into a system-level environment to estimate the impact of using CNT global interconnects on the overall performance of several multi-core chip multiprocessor (CMP) applications. Our results indicate that MWCNTs can provide the most significant performance speedup among the CNT alternatives (up to 1.9x) over Cu global interconnects. With further improvements in CNT fabrication technology, it is shown that mixed SWCNT/MWCNT bundles and SWCNT bundles can also become viable global interconnect alternatives.

[1]  Narayanan Vijaykrishnan,et al.  Assessing Carbon Nanotube Bundle Interconnect for Future FPGA Architectures , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[2]  Nikil D. Dutt,et al.  Fast exploration of bus-based communication architectures at the CCATB abstraction , 2008, TECS.

[3]  Sachin S. Sapatnekar,et al.  Designing optimized pipelined global interconnects: algorithms and methodology impact , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[4]  Igor L. Markov,et al.  Fixed-outline floorplanning: enabling hierarchical design , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[5]  J.-Q. Lu,et al.  Densification of Carbon Nanotube Bundles for Interconnect Application , 2007, 2007 IEEE International Interconnect Technology Conferencee.

[6]  G. Duesberg,et al.  Carbon nanotubes for interconnect applications , 2002, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[7]  P. Ajayan,et al.  Reliability and current carrying capacity of carbon nanotubes , 2001 .

[8]  Wei Wang,et al.  Analyzing Conductance of Mixed Carbon-Nanotube Bundles for Interconnect Applications , 2007, IEEE Electron Device Letters.

[9]  K. Roy,et al.  A circuit model for carbon nanotube interconnects: comparative study with Cu interconnects for scaled technologies , 2004, ICCAD 2004.

[10]  T. Kuan,et al.  Alteration of Cu conductivity in the size effect regime , 2004 .

[11]  P. Burke,et al.  Quantitative theory of nanowire and nanotube antenna performance , 2004, IEEE Transactions on Nanotechnology.

[12]  A. Naeemi,et al.  Physical Modeling of Temperature Coefficient of Resistance for Single- and Multi-Wall Carbon Nanotube Interconnects , 2007, IEEE Electron Device Letters.

[13]  Eby G. Friedman,et al.  Optimum wire sizing of RLC interconnect with repeaters , 2003, GLSVLSI '03.

[14]  J. Meindl,et al.  Design and Performance Modeling for Single-Walled Carbon Nanotubes as Local, Semiglobal, and Global Interconnects in Gigascale Integrated Systems , 2007, IEEE Transactions on Electron Devices.

[15]  Anoop Gupta,et al.  The SPLASH-2 programs: characterization and methodological considerations , 1995, ISCA.

[16]  A. Kawabata,et al.  Novel approach to fabricating carbon nanotube via interconnects using size-controlled catalyst nanoparticles , 2006, 2006 International Interconnect Technology Conference.

[17]  M. Dresselhaus,et al.  Carbon nanotubes : synthesis, structure, properties, and applications , 2001 .

[18]  P. Burke.  Luttinger liquid theory as a model of the gigahertz electrical properties of carbon nanotubes , 2002 .

[19]  H. Dai,et al.  Can we achieve ultra-low resistivity in carbon nanotube-based metal composites? , 2004 .

[20]  Kaustav Banerjee,et al.  Performance analysis of carbon nanotube interconnects for VLSI applications , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[21]  A. Zettl,et al.  Thermal conductivity of single-walled carbon nanotubes , 1998 .

[22]  Lawrence T. Pileggi,et al.  Inductance 101: modeling and extraction , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[23]  D. Rossi,et al.  Modeling Crosstalk Effects in CNT Bus Architectures , 2007, IEEE Transactions on Nanotechnology.

[24]  Reza Sarvari,et al.  Performance Modeling and Optimization for Single- and Multi-Wall Carbon Nanotube Interconnects , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[25]  Arthur Nieuwoudt,et al.  Assessing the Implications of Process Variations on Future Carbon Nanotube Bundle Interconnect Solutions , 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

[26]  E. H. Sondheimer,et al.  The mean free path of electrons in metals , 1952 .

[27]  Yehea I. Ismail,et al.  Effects of inductance on the propagation delay and repeater insertion in VLSI circuits: A summary , 1999, IEEE Circuits and Systems Magazine.

[28]  C.P. Wong,et al.  Assembling Carbon Nanotube Bundles Using Transfer Process for Fine-Pitch Electrical Interconnect Applications , 2007, 2007 Proceedings 57th Electronic Components and Technology Conference.

[29]  Arthur Nieuwoudt,et al.  Predicting the Performance and Reliability of Carbon Nanotube Bundles for On-Chip Interconnect , 2007, 2007 Asia and South Pacific Design Automation Conference.

[30]  M. Shatzkes,et al.  Electrical-Resistivity Model for Polycrystalline Films: the Case of Arbitrary Reflection at External Surfaces , 1970 .

[31]  S. Wong,et al.  Physical modeling of spiral inductors on silicon , 2000 .

[32]  M. Meyyappan,et al.  Bottom-up approach for carbon nanotube interconnects , 2003 .

[33]  Mei Liu,et al.  Inductance of mixed carbon nanotube bundles , 2007 .

[34]  Kyung-Hoae Koo,et al.  Modeling of the performance of carbon nanotube bundle, cu/low-k and optical on-chip global interconnects , 2007, SLIP '07.

[35]  P. Avouris,et al.  Multishell conduction in multiwalled carbon nanotubes , 2002 .

[36]  Nikil D. Dutt,et al.  Extending the transaction level modeling approach for fast communication architecture exploration , 2004, Proceedings. 41st Design Automation Conference, 2004..

[37]  Kaushik Roy,et al.  Modeling of metallic carbon-nanotube interconnects for circuit simulations and a comparison with Cu interconnects for scaled technologies , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.