Hardware Security and Trust: Logic Locking as a Design-for-Trust Solution

Ever-increasing design complexity and the skyrocketing cost of setting up a foundry have led to the globalization of the integrated circuit (IC) supply chain. A globalized and distributed IC supply fosters security threats such as reverse engineering, piracy, and hardware Trojans, and forces the stakeholders to revisit the trust at various steps in the IC design and fabrication flow. Among the ensemble of solutions proposed to address hardware-related trust issues, logic locking has gained significant interest from the research community. A series of defense techniques and attacks have been developed over the past few years. This chapter presents a comprehensive survey of recent research efforts in the field of logic locking. The emphasis is on the subtle difference between the logic locking attacks/countermeasures in terms of the threat models employed and strengths/vulnerabilities of existing logic locking techniques.

[1]  Miodrag Potkonjak,et al.  Watermarking techniques for intellectual property protection , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[2]  Jarrod A. Roy,et al.  Ending Piracy of Integrated Circuits , 2010, Computer.

[3]  Jeyavijayan Rajendran,et al.  Regaining Trust in VLSI Design: Design-for-Trust Techniques , 2014, Proceedings of the IEEE.

[4]  Joseph Zambreno,et al.  Preventing IC Piracy Using Reconfigurable Logic Barriers , 2010, IEEE Design & Test of Computers.

[5]  Dick James,et al.  The state-of-the-art in semiconductor reverse engineering , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

[6]  Lilian Bossuet,et al.  Survey of hardware protection of design data for integrated circuits and intellectual properties , 2014, IET Comput. Digit. Tech..

[7]  Nur A. Touba,et al.  Improving logic obfuscation via logic cone analysis , 2015, 2015 16th Latin-American Test Symposium (LATS).

[8]  Jeyavijayan Rajendran,et al.  Security analysis of integrated circuit camouflaging , 2013, CCS.

[9]  Miodrag Potkonjak,et al.  Effective iterative techniques for fingerprinting design IP , 1999, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Michael S. Hsiao,et al.  Hardware Trojan Attacks: Threat Analysis and Countermeasures , 2014, Proceedings of the IEEE.

[11]  Ozgur Sinanoglu,et al.  Evolution of logic locking , 2017, 2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

[12]  Swarup Bhunia,et al.  Security against hardware Trojan through a novel application of design obfuscation , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[13]  Ankur Srivastava,et al.  Mitigating SAT Attack on Logic Locking , 2016, CHES.

[14]  Siva Sai Yerubandi,et al.  Differential Power Analysis , 2002 .

[15]  Jeyavijayan Rajendran,et al.  Security analysis of logic obfuscation , 2012, DAC Design Automation Conference 2012.

[16]  Oded Goldreich Foundations of Cryptography: Index , 2001 .

[17]  Giorgio Di Natale,et al.  A novel hardware logic encryption technique for thwarting illegal overproduction and Hardware Trojans , 2014, 2014 IEEE 20th International On-Line Testing Symposium (IOLTS).

[18]  Igor L. Markov,et al.  Solving the Third-Shift Problem in IC Piracy With Test-Aware Logic Locking , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[19]  Meng Li,et al.  Cyclic Obfuscation for Creating SAT-Unresolvable Circuits , 2017, ACM Great Lakes Symposium on VLSI.

[20]  Jeyavijayan Rajendran,et al.  Security analysis of Anti-SAT , 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

[21]  Sayak Ray,et al.  Evaluating the security of logic encryption algorithms , 2015, 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

[22]  Swarup Bhunia,et al.  HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[23]  Jeyavijayan Rajendran,et al.  Removal Attacks on Logic Locking and Camouflaging Techniques , 2020, IEEE Transactions on Emerging Topics in Computing.

[24]  Jeyavijayan Rajendran,et al.  Provably-Secure Logic Locking: From Theory To Practice , 2017, CCS.

[25]  Ramesh Karri,et al.  A Primer on Hardware Security: Models, Methods, and Metrics , 2014, Proceedings of the IEEE.

[26]  Mark Mohammad Tehranipoor,et al.  Trustworthy Hardware: Identifying and Classifying Hardware Trojans , 2010, Computer.

[27]  Neil Walkinshaw,et al.  Reverse-Engineering Software Behavior , 2013, Adv. Comput..

[28]  Jarrod A. Roy,et al.  EPIC: Ending Piracy of Integrated Circuits , 2008, 2008 Design, Automation and Test in Europe.

[29]  Jeyavijayan Rajendran,et al.  Logic encryption: A fault analysis perspective , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[30]  Domenic Forte,et al.  Novel Bypass Attack and BDD-based Tradeoff Analysis Against All Known Logic Locking Attacks , 2017, CHES.

[31]  Jeyavijayan Rajendran,et al.  Fault Analysis-Based Logic Encryption , 2015, IEEE Transactions on Computers.

[32]  Farinaz Koushanfar,et al.  Integrated circuits metering for piracy protection and digital rights management: an overview , 2011, GLSVLSI '11.

[33]  Oded Goldreich,et al.  Foundations of Cryptography: List of Figures , 2001 .

[34]  Ozgur Sinanoglu,et al.  Security analysis of logic encryption against the most effective side-channel attack: DPA , 2015, 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS).

[35]  Meng Li,et al.  AppSAT: Approximately deobfuscating integrated circuits , 2017, 2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

[36]  Mark Mohammad Tehranipoor,et al.  Counterfeit Integrated Circuits: A Rising Threat in the Global Semiconductor Supply Chain , 2014, Proceedings of the IEEE.

[37]  Ramesh Karri,et al.  On Improving the Security of Logic Locking , 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[38]  Hai Zhou,et al.  Double DIP: Re-Evaluating Security of Logic Encryption Algorithms , 2017, ACM Great Lakes Symposium on VLSI.

[39]  Ozgur Sinanoglu,et al.  SARLock: SAT attack resistant logic locking , 2016, 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

[40]  Jeyavijayan Rajendran,et al.  What to Lock?: Functional and Parametric Locking , 2017, ACM Great Lakes Symposium on VLSI.

[41]  Jeyavijayan Rajendran,et al.  Activation of logic encrypted chips: Pre-test or post-test? , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[42]  Oded Goldreich,et al.  On the foundations of cryptography , 2019, Providing Sound Foundations for Cryptography.