论文信息 - An L-band CMOS frequency doubler using a time-delay technique

An L-band CMOS frequency doubler using a time-delay technique

In this paper, a frequency doubler circuit is presented that converts a 0.6 GHz signal to a 1.2 GHz output using standard CMOS 0.18 mum technology. The proposed circuit uses a time-delay element and an XOR logic gate to perform the frequency multiplication and is implemented entirely on-chip. Advantages of this topology include good fundamental suppression, compact layout, and low power consumption. Experimental results show a relatively constant output power of approximately 4 dBm with an input power from -3 dBm to 10 dBm, fundamental and third order harmonic suppressions of up to -30 dBc and a power consumption of 9 mW. The phase noise of the output signal is -117 dBc at a 500 kHz offset

B.R. Jackson | C.E. Saavedra

[1] Zvonko G. Vranesic,et al. Fundamentals of Digital Logic with VHDL Design , 2008 .

[2] Youngkou Lee,et al. Clock multiplier using digital CMOS standard cells for high-speed digital communication systems , 1999 .

[3] Sang-Gug Lee,et al. Low power fully differential frequency doubler , 2003 .

[4] F. Ellinger,et al. Ultracompact SOI CMOS frequency doubler for low power applications at 26.5-28.5 GHz , 2004, IEEE Microwave and Wireless Components Letters.

[5] H.C. Luong,et al. A 1.5-V 4-GHz dynamic-loading regenerative frequency doubler in a 0.35-/spl mu/m CMOS process , 2002, 2002 IEEE MTT-S International Microwave Symposium Digest (Cat. No.02CH37278).

[6] C.E. Saavedra,et al. A clock frequency doubler using a passive integrator and emitter-coupled comparator circuit , 2004, Canadian Conference on Electrical and Computer Engineering 2004 (IEEE Cat. No.04CH37513).