Scheduling of a LQ Control Algorithm for Efficient FPGA Implementation

Abstract This paper deals with the speed optimization of iterative algorithms with matrix operations or nested loops for hardware implementation in Field Programmable Gate Arrays (FPGA). The presented scheduling algorithm use Integer Linear Programming (ILP) while complex algorithm structure is modeled by system of linear inequalities. The method is demonstrated on a LQ control algorithm. An advantage of the presented scheduling method is its suitability for algorithms with longer iteration period.

[1]  Sabih H. Gerez,et al.  An Integer Linear Programming Approach to the Overlapped Scheduling of Iterative Data-Flow Graphs for Target Architectures with Communication Delays , 2000 .

[2]  Premysl Sucha,et al.  Scheduling of Iterative Algorithms with Matrix Operations for Efficient FPGA Design—Implementation of Finite Interval Constant Modulus Algorithm , 2007, J. VLSI Signal Process..

[3]  Claire Hanen,et al.  A Study of the Cyclic Scheduling Problem on Parallel Processors , 1995, Discret. Appl. Math..

[4]  Keshav Pingali,et al.  Tiling Imperfectly-nested Loop Nests (REVISED) , 2000 .

[5]  Philip H. Sweany,et al.  Improving software pipelining with unroll-and-jam , 1996, Proceedings of HICSS-29: 29th Hawaii International Conference on System Sciences.

[6]  R. E. Kalman,et al.  Contributions to the Theory of Optimal Control , 1960 .

[7]  Alain Darte,et al.  Loop Shifting for Loop Compaction , 1999, LCPC.

[8]  Rajesh Gupta,et al.  Loop shifting and compaction for the high-level synthesis of designs with complex control flow , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[9]  B. Ramakrishna Rau,et al.  Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing , 1981, MICRO 14.

[10]  Keshav Pingali,et al.  Tiling Imperfectly-nested Loop Nests , 2000, ACM/IEEE SC 2000 Conference (SC'00).

[11]  Dirk Fimmel,et al.  Optimal Software Pipelining Under Resource Constraints , 2001, Int. J. Found. Comput. Sci..

[12]  Premysl Sucha,et al.  Performance tuning of iterative algorithms in signal processing , 2005, International Conference on Field Programmable Logic and Applications, 2005..

[13]  Randolph E. Harr,et al.  Efficient pipelining of nested loops: unroll-and-squash , 2002, Proceedings 16th International Parallel and Distributed Processing Symposium.

[14]  Phillip A. Regalia,et al.  Architecture design for FPGA implementation of finite interval CMA , 2004, 2004 12th European Signal Processing Conference.

[15]  Wonyong Sung,et al.  Combined word-length optimization and high-level synthesis ofdigital signal processing systems , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  Michael Wolfe,et al.  High performance compilers for parallel computing , 1995 .

[17]  Jirí Kadlec,et al.  Logarithmic Number System and Floating-Point Arithmetics on FPGA , 2002, FPL.

[18]  Premysl Sucha,et al.  Scheduling of iterative algorithms on FPGA with pipelined arithmetic unit , 2004, Proceedings. RTAS 2004. 10th IEEE Real-Time and Embedded Technology and Applications Symposium, 2004..