Efficient Self-Recovering ASIC Design
暂无分享,去创建一个
[1] Miodrag Potkonjak,et al. Behavioral-level synthesis of heterogeneous BISR reconfigurable ASIC's , 1998, IEEE Trans. Very Large Scale Integr. Syst..
[2] Miodrag Potkonjak,et al. Configurable spare processors: a new approach to system level fault-tolerance , 1996, Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
[3] Alex Orailoglu,et al. Microarchitectural synthesis of ICs with embedded concurrent fault isolation , 1997, Proceedings of IEEE 27th International Symposium on Fault Tolerant Computing.
[4] Krishan K. Sabnani,et al. Spare Capacity as a Means of Fault Detection and Diagnosis in Multiprocessor Systems , 1989, IEEE Trans. Computers.
[5] Ramesh Karri,et al. Coactive scheduling and checkpoint determination during high level synthesis of self-recovering microarchitectures , 1994, IEEE Trans. Very Large Scale Integr. Syst..
[6] Amber Roy-Chowdhury,et al. Compiler-assisted generation of error-detecting parallel programs , 1996, Proceedings of Annual Symposium on Fault Tolerant Computing.
[7] Ramesh Karri,et al. Automatic Synthesis of Self-Recovering VLSI Systems , 1996, IEEE Trans. Computers.
[8] José A. B. Fortes,et al. The Full-Use-of-Suitable-Spares (FUSS) Approach to Hardware Reconfiguration for Fault-Tolerant Processor Arrays , 1990, IEEE Trans. Computers.
[9] Ramesh Karri,et al. Introspection: a low overhead binding technique during self-diagnosing microarchitecture synthesis , 1996, 33rd Design Automation Conference Proceedings, 1996.
[10] Niraj K. Jha,et al. Partitioned Encoding Schemes for Algorithm-Based Fault Tolerance in Massively Parallel Systems , 1994, IEEE Trans. Parallel Distributed Syst..
[11] Alex Orailoglu. Microarchitectural synthesis of gracefully degradable, dynamically reconfigurable ASICs , 1996, Proceedings International Conference on Computer Design. VLSI in Computers and Processors.
[12] Fadi J. Kurdahi,et al. Optimal algorithms for recovery point insertion in recoverable microarchitectures , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..