Random Walk Guided Decap Embedding for Power/Ground Network Optimization

The reliability of power/ground networks is becoming significantly important in modern integrated circuits, while decap insertion is a main approach to enhance the power grid safety. In this brief, we propose a fast and efficient decap allocation algorithm, and adequately consider the leakage effect of decap. This approach borrows the idea of random walks to perform circuit partitioning and does subsequent decap insertion based on locality property of partitioned area, which avoids solving a large nonlinear programming problem in traditional decap optimization process. The optimization flow also integrates a refined leakage current model for decaps which makes it more practical. Experimental results show that our proposed method can achieve approximate 15 X speed up over the optimal budget method within the acceptable error tolerance. Also this algorithm only causes a few penalty area to compensate the leakage effect.

[1]  Yici Cai,et al.  Partitioning-based approach to fast on-chip decap budgeting and minimization , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[2]  Sanjay Pant,et al.  Power Grid Physics and Implications for CAD , 2007, IEEE Design & Test of Computers.

[3]  Rajendran Panda,et al.  Hierarchical analysis of power distribution networks , 2000, DAC.

[4]  Sani R. Nassif,et al.  Random walks in a supply network , 2003, DAC '03.

[5]  Sachin S. Sapatnekar,et al.  Hierarchical random-walk algorithms for power grid analysis , 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

[6]  Sheldon X.-D. Tan,et al.  Partial random walk for large linear network analysis , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[7]  Ernest S. Kuh,et al.  Power and ground network topology optimization for cell based VLSIs , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[8]  Sani R. Nassif,et al.  An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts , 2002, ISPD '02.

[9]  Charlie Chung-Ping Chen,et al.  HiPRIME: hierarchical and passivity preserved interconnect macromodeling engine for RLKC power delivery , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Chung-Kuan Cheng,et al.  Area minimization of power distribution network using efficient nonlinear programming techniques , 2001, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Eli Chiprout Fast flip-chip power grid analysis via locality and grid shells , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[12]  Yici Cai,et al.  A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery , 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

[13]  B. Beker,et al.  Modeling of power distribution systems for high-performance microprocessors , 1999 .

[14]  Mahmut T. Kandemir,et al.  Leakage Current: Moore's Law Meets Static Power , 2003, Computer.

[15]  Yici Cai,et al.  Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk Approach , 2007, 2007 Asia and South Pacific Design Automation Conference.