For a globally asynchronous locally synchronous (GALS) system, data transfer mechanisms based on a current-mode multiple valued logic (CMMVL) has been studied to reduce complexity and power dissipation of wires. However, these schemes consume considerable amount of power even in idle states because of the static power caused by their inherent structure. In this paper, new encoder and decoder circuits using CMMVL are suggested to reduce the static power. The effectiveness of the proposed data transfer is validated by comparisons with the previous CMMVL scheme and conventional voltage-mode schemes such as dual-rail and 1-of-4 encodings through simulation with a 0.25-μm CMOS technology. Simulation results demonstrate that the proposed CMMVL scheme significantly reduces power consumption of the previous one and is superior to dual-rail and 1-of-4 schemes over wire length of 2 mm and 4 mm, respectively.
[1]
Andrew Lines,et al.
Asynchronous interconnect for synchronous SoC design
,
2004,
IEEE Micro.
[2]
Steve Furber,et al.
Principles of Asynchronous Circuit Design: A Systems Perspective
,
2010
.
[3]
Dong-Soo Har,et al.
Low Delay-Power Product Current-Mode Multiple Valued Logic for Delay-Insensitive Data Transfer Mechanism
,
2005,
IEICE Trans. Fundam. Electron. Commun. Comput. Sci..
[4]
William John Bainbridge,et al.
Delay insensitive system-on-chip interconnect using 1-of-4 data encoding
,
2001,
Proceedings Seventh International Symposium on Asynchronous Circuits and Systems. ASYNC 2001.