Time-based Digital LDO Regulator

This paper presents a digital LDO (DLDO) regulator utilizing a time-based comparator rather than a voltage-based comparator in order to exploit the advantages of time domain and produce a more robust regulator. The time-based comparator compares between the reference and the load voltage levels and generates a digital bit that turns on/off the PMOS power switch. It consists of three main blocks: starved inverter, phase detector and SR latch. The starved inverter acts as a voltage to time converter where it converts both reference and load voltages into time waveforms. Then, the phase detector detects the difference between the two voltage values and generates a digital signal that enables the SR latch. Finally, the SR latch activates/deactivates the PMOS power switch to support the desired load voltage level. The time-based DLDO has an input voltage range between 0.8V and 0.6V and generates a load voltage range between 0.7V to 0.5V for a load current between $50\mu \mathrm{A}$ and $300\mu \mathrm{A}$. The design is done in 65nm TSMC. The detailed simulation results confirmed a peak current efficiency of 99% by consuming a quiescent current of $1 \mu \mathrm{A}$ at $V_{L}=0.5\mathrm{V}$. The load transient response time of $2.4\mathrm{ns}$ at $V_{L}=0.7\mathrm{V}$

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