Circuit design of 2-input reconfigurable dynamic logic based on stacked type Fe-FET with whole set of 16 functions

Circuit design of 2-input reconfigurable dynamic logic based on stacked type Fe-FET with the whole set of 16 functions has been newly described. This structure can be realized with low cost process technology of 3D NAND flash memory. By replacing +V for substrate to D-type Fe-FET and 0 for substrate to E-type Fe-FET logic generation part of newly proposed scheme can be realized with only 2 silicon pillars. This number of silicon pillars is only 1/3 compared with that of previously proposed conventional 16 function 12T DRDLC with two states (+V, 0) of control gate voltages scheme. By using process technology of 3D NAND flash memory low cost high density reconfigurable LSI will be realized with newly proposed scheme.

[1]  Dong Woo Kim,et al.  Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra high density NAND flash memory , 2006, 2009 Symposium on VLSI Technology.

[2]  Shigeyoshi Watanabe,et al.  Proposal of Vertical Stacked Type Fe-FET NAND/NAND Array and Its Application to Logic LSI , 2016 .

[3]  Heinz-Gerd Zimmer.  Johannes Müller , 2006, Clinical cardiology.

[4]  Shigeyoshi Watanabe,et al.  New Design Technology of Independent-Gate Controlled Double-Gate Transistor for System LSI , 2009 .

[5]  C. Tretz,et al.  High-Density Reduced-Stack Logic Circuit Techniques Using Independent-Gate Controlled Double-Gate Devices , 2006, IEEE Transactions on Electron Devices.

[6]  Shigeyoshi Watanabe,et al.  Proposal of Stacked Type Memory/Logic Circuit Array and Its Application to LUT (Look Up Table) , 2016 .

[7]  Kartik Mohanram,et al.  Dual-$V_{th}$ Independent-Gate FinFETs for Low Power Logic Circuits , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Shigeyoshi Watanabe,et al.  Analysis of bit cost for stacked type MRAM with NAND structured cell , 2013 .

[9]  Hiroshima Yu,et al.  New design technology of Independent-Gate controlled Stacked type 3D transistor for system LSI , 2008 .

[10]  I. Hassoune,et al.  Double-gate MOSFET based reconfigurable cells , 2007 .

[11]  Fumio Horiguchi,et al.  Effects of a new trench-isolated transistor using sidewall gates , 1989 .

[12]  Manabu Kobayashi,et al.  Circuit Design of 2-Input Reconfigurable Dynamic Logic Based on Double Gate MOSFETs with Whole Set of 16 Functions , 2014 .

[13]  Shinsugita-cho Isogo-ku,et al.  Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory , 2007 .