Hybrid triple-level-cell/multi-level-cell NAND flash storage array with chip exchangeable method

This paper proposes a mix-and-match design method for triple level cell (TLC)/multi level cell (MLC) NAND flash hybrid and exchangeable storage arrays. A TLC-NAND flash provides an low cost and high capacity memory solution. However the reliability and access latency of TLC NAND flash are degraded from MLC NAND flash. Additionally, the block unit write is preferable for TLC NAND flash since the write order is complicated due to narrow data margin and write disturbance. The proposed solution combines TLC and MLC NAND flash memories for a storage array. To reduce access to TLC NAND flash, the stored data is screened and only the static frozen data are stored into TLC NAND flash with a Round-Robin frozen data collection algorithm (RR-FDCA). Furthermore, the proposed chip exchanging method extends the solid-state drive (SSD) lifetime without system suspending. As a result, in spite of moderate characteristics of TLC NAND flash, the proposed storage array can achieve 29% write energy saving and 56% write performance enhancement with 17% cost reduction, compared with the conventional MLC-only SSD.

[1]  Tadahiro Kuroda,et al.  A 2.5Gb/s/ch 4PAM inductive-coupling transceiver for non-contact memory card , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[2]  Shinya Nakano,et al.  A 7Gb/s/link non-contact memory module for multi-drop bus system using energy-equipartitioned coupled transmission line , 2012, 2012 IEEE International Solid-State Circuits Conference.

[3]  Ken Takeuchi,et al.  SCM capacity and NAND over-provisioning requirements for SCM/NAND flash hybrid enterprise SSD , 2013, 2013 5th IEEE International Memory Workshop.

[4]  Myounggon Kang,et al.  Improving Read Disturb Characteristics by Using Double Common Source Line and Dummy Switch Architecture in Multi Level Cell NAND Flash Memory with Low Power Consumption , 2011 .

[5]  Massimo Rossini,et al.  A 3bit/cell 32Gb NAND flash memory at 34nm with 6MB/s program throughput and with dynamic 2b/cell blocks configuration mode for a program throughput increase up to 13MB/s , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[6]  M. Higashitani,et al.  A novel self-aligned shallow trench isolation cell for 90 nm 4 Gbit NAND flash EEPROMs , 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

[7]  Ken Takeuchi,et al.  x11 performance increase, x6.9 endurance enhancement, 93% energy reduction of 3D TSV-integrated hybrid ReRAM/MLC NAND SSDs by data fragmentation suppression , 2012, 2012 Symposium on VLSI Circuits (VLSIC).

[8]  Joon-Sung Yang,et al.  Bit-error rate improvement of TLC NAND Flash using state re-ordering , 2012, IEICE Electron. Express.

[9]  Sung Min Kim,et al.  A stacked memory device on logic 3D technology for ultra-high-density data storage , 2011, Nanotechnology.

[10]  Shuhei Tanakamaru,et al.  Unified solid-state-storage architecture with NAND flash memory and ReRAM that tolerates 32× higher BER for big-data applications , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[11]  T. Kamei,et al.  A 56nm CMOS 99mm2 8Gb Multi-level NAND Flash Memory with 10MB/s Program Throughput , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[12]  T.D. Pham,et al.  A 146 mm/sup 2/ 8 Gb NAND flash memory with 70 nm CMOS technology , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[13]  N. Shibata,et al.  A 70nm 16Gb 16-level-cell NAND Flash Memory , 2007, 2007 IEEE Symposium on VLSI Circuits.