An efficient layout style for two-metal CMOS leaf cells and its automatic synthesis

A layout style that enables either an automatic layout synthesizer or a layout designer to take full advantage of the second metal layer available from today's technology is proposed. The style not only facilitates power/ground diffusion overlapping but also simplifies the intracell routing problem by having power/ground in the middle and routing in the upper and the lower constraint-free regions. An automatic leaf cell layout synthesizer, called THEDA.P, that is based on the proposed style has been implement. Using the same transistor placement algorithm, THEDA.P outperforms a synthesizer based on T. Uehara and W.M. van Cleemput's (1981) approach by almost 20% in layout compactness across a wide range of small-scale integrated circuits. THEDA.P has been used to build a standard cell library that was previously handcrafted. Results from designing two modules show that THEDA.P's layout quality is very competitive. >

[1]  Sung-Mo Kang.  Metal--Metal Matrix (M /sup 3/) for High-Speed MOS VLSI Layout , 1987, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Takashi Satoh,et al.  A high packing density module generator for CMOS logic cells , 1988, DAC '88.

[3]  Chi-Yuan Lo,et al.  GENAC: An Automatic Cell Synthesis Tool , 1989, 26th ACM/IEEE Design Automation Conference.

[4]  Daniel Gajski,et al.  LES: a layout expert system , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  A.D. Lopez,et al.  A Dense Gate Matrix Layout Method for MOS VLSI , 1980, IEEE Journal of Solid-State Circuits.

[6]  P. K. Sun.  CETUS-a versatile custom cell synthesizer , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[7]  Akihiro Hashimoto,et al.  Wire routing by optimizing channel assignment within large apertures , 1971, DAC.

[8]  Sarma Sastry,et al.  Flexible transistor matrix (FTM) , 1991, 28th ACM/IEEE Design Automation Conference.

[9]  Donald G. Baltus,et al.  SOLO: a generator of efficient layouts from optimized MOS circuit schematics , 1988, DAC '88.

[10]  Reuven Bar-Yehuda,et al.  Depth-first-search and dynamic programming algorithms for efficient CMOS cell generation , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  C. C. Chen,et al.  The Layout Synthesizer: An Automatic Netlist-to-Layout System , 1989, 26th ACM/IEEE Design Automation Conference.

[12]  Antun Domic,et al.  CLEO: a CMOS layout generator , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[13]  H. De Man,et al.  A Flexible Module Library for Custom DSP Applications in a Multiprocessor Environment , 1989, ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference.

[14]  Dwight D. Hill,et al.  Placement algorithms for CMOS cell synthesis , 1990, Proceedings., 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[15]  Charles J. Poirier.  Excellerator: custom CMOS leaf cell layout generator , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  Yu-Chin Hsu,et al.  LiB: a CMOS cell compiler , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[17]  Mary Jane Irwin,et al.  A Comparison of Four Two-Dimensional Gate Matrix Layout Tools , 1989, 26th ACM/IEEE Design Automation Conference.

[18]  Brian W. Kernighan,et al.  An efficient heuristic procedure for partitioning graphs , 1970, Bell Syst. Tech. J..

[19]  Jin Kim,et al.  TALIB: An IC Layout Design Assistant , 1983, AAAI.

[20]  Yu-Chin Hsu,et al.  A fast transistor-chaining algorithm for CMOS cell layout , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[21]  Ron Y. Pinter,et al.  Optimal Chaining of CMOS Transistors in a Functional Cell , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[22]  Uehara,et al.  Optimal Layout of CMOS Functional Arrays , 1981 .

[23]  Grant Martin,et al.  Transistor placement and interconnect algorithms for leaf cell synthesis , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

[24]  John P. Hayes,et al.  Layout optimization of static CMOS functional cells , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[25]  Kurt Keutzer.  DAGON: Technology Binding and Local Optimization by DAG Matching , 1987, DAC.

[26]  Dennis V. Heinbuch,et al.  CMOS3 cell library , 1988 .

[27]  C. Y. Roger Chen,et al.  A new layout optimization methodology for CMOS complex gates , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[28]  Jan Madsen.  A new approach to optimal cell synthesis , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[29]  P. W. Kollaritsch,et al.  TOPOLOGIZER: An Expert System Translator of Transistor Connectivity to Symbolic Cell Layout , 1984, ESSCIRC '84: Tenth European Solid-State Circuits Conference.