A compact effective-current model for power performance analysis on state-of-the-art technology development and benchmarking

Advances in semiconductor technology have enabled significant performance improvements over the past several decades. However, at the current pace of the development of semiconductor technology, it is increasingly important to achieve a proper balance between performance improvement and power consumption. In this study, to quantitatively analyze the performance and power consumption of new technologies, a compact effective-current model is proposed and used for power performance analysis (PPA). The PPA is performed by separately varying several device characteristics such as drain-induced barrier lowering (DIBL), mobility, and threshold voltage (VT) to determine which options can provide more benefits and better balance for new technologies. The analysis results indicate that the performance improvement due to DIBL reduction (especially below 20 mV/V) is limited. However, VT engineering has more advantages than DIBL and mobility enhancement, unless threshold voltage scaling induces leakage current degradation. Otherwise, mobility enhancement is the most attractive method. By using the proposed compact effective-current model for PPA, we enabled the effective and quantitative estimation of the benefits in terms of performance and power consumption.

[1]  K. Yahashi,et al.  Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm fin width and 20 nm gate length , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[2]  Adrian M. Ionescu,et al.  Tunnel field-effect transistors as energy-efficient electronic switches , 2011, Nature.

[3]  X. Chen,et al.  A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process , 2008, 2008 Symposium on VLSI Technology.

[4]  Resve A. Saleh,et al.  Generalized Power-Delay Metrics in Deep Submicron CMOS Designs , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Michael Gschwind,et al.  New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors , 2003, IBM J. Res. Dev..

[6]  D.A. Antoniadis,et al.  MOSFET Performance Scaling—Part I: Historical Trends , 2008, IEEE Transactions on Electron Devices.

[7]  Jun Luo,et al.  Mobility Enhancement Technology for Scaling of CMOS Devices: Overview and Status , 2011 .

[8]  Mohamed I. Elmasry,et al.  Design and optimization of multithreshold CMOS (MTCMOS) circuits , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Anantha P. Chandrakasan,et al.  Minimizing power consumption in digital CMOS circuits , 1995, Proc. IEEE.

[10]  Shien-Yang Wu,et al.  A 16nm FinFET CMOS technology for mobile SoC and computing applications , 2013 .

[11]  Geoffrey Yeap,et al.  Smart mobile SoCs driving the semiconductor industry: Technology trend, challenges and opportunities , 2013, 2013 IEEE International Electron Devices Meeting.

[12]  E.J. Nowak,et al.  Improved effective switching current (IEFF+) and capacitance methodology for CMOS circuit performance prediction and model-to-hardware correlation , 2008, 2008 IEEE International Electron Devices Meeting.

[13]  T. Schulz,et al.  An Effective Switching Current Methodology to Predict the Performance of Complex Digital Circuits , 2007, 2007 IEEE International Electron Devices Meeting.

[14]  Thomas D. Burd,et al.  Energy efficient CMOS microprocessor design , 1995, Proceedings of the Twenty-Eighth Annual Hawaii International Conference on System Sciences.

[15]  J. Kavalieros,et al.  100 nm gate length high performance/low power CMOS transistor structure , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[16]  Mark Y. Liu,et al.  A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size , 2014, 2014 IEEE International Electron Devices Meeting.

[17]  Yuan Taur,et al.  CMOS design near the limit of scaling , 2002 .

[18]  A.P. Chandrakasan,et al.  Dual-threshold voltage techniques for low-power digital circuits , 2000, IEEE Journal of Solid-State Circuits.

[19]  Martin M. Frank.  High-k / metal gate innovations enabling continued CMOS scaling , 2011 .

[20]  J. Mazurier,et al.  14nm FDSOI technology for high speed and energy efficient applications , 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

[22]  S. Datta,et al.  Effective Capacitance and Drive Current for Tunnel FET (TFET) CV/I Estimation , 2009, IEEE Transactions on Electron Devices.

[23]  A. Mercha,et al.  Group IV channels for 7nm FinFETs: Performance for SoCs power and speed metrics , 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

[24]  S. Datta,et al.  Can the subthreshold swing in a classical FET be lowered below 60 mV/decade? , 2008, 2008 IEEE International Electron Devices Meeting.

[25]  R. Chau,et al.  Benchmarking nanotechnology for high-performance and low-power logic transistor applications , 2004, IEEE Transactions on Nanotechnology.