Transmission Gate and Hybrid Cmos Full Adder Characterization and Power-Delay Product Estimation Based on Mathematical Model

Abstract The demand for low power CMOS VLSI circuit design is increasing due to the ever-increasing demand for portable devices. A Full Adder (FA) is the basic building block of many VLSI subsystems, and it affects the performance of VLSI subsystems. The Transmission Gate (TG) and hybrid CMOS FA designs can achieve low Power Delay Product (PDP) compared to other FA designs, hence these FA designs are suitable for portable devices. A large number of repetitive simulations are required for thorough characterization of the FA design. A method to develop the mathematical model (based on 2nd degree polynomial equation) of the FA is proposed here, which satisfactorily estimates the Power Delay Product (PDP) of TG and hybrid CMOS FAs for non-simulated parameter combinations within given parameter range. Main aim of proposed method is to reduce characterization effort by estimating PDP using mathematical model, rather than estimating it through simulation. Also, mathematical model can be used to estimate the transistor widths to achieve low PDP for particular operating condition. Further, the effect of individual polynomial term, number of parameters, and number of points per parameter, on the accuracy of mathematical model is also studied.

[1]  Dinesh Manocha,et al.  SOLVING SYSTEMS OF POLYNOMIAL EQUATIONS , 2002 .

[2]  Mónico Linares Aranda,et al.  CMOS Full-Adders for Energy-Efficient Arithmetic Applications , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  Mariano Aguirre,et al.  An Alternative Logic Approach to Implement High-Speed Low-Power Full Adder Cells , 2005, 2005 18th Symposium on Integrated Circuits and Systems Design.

[4]  J. V. R. Ravindra,et al.  Power Aware and Delay Efficient Hybrid CMOS Full-Adder for Ultra Deep Submicron Technology , 2013, 2013 European Modelling Symposium.

[5]  Mazad Zaveri,et al.  A low-power high-speed hybrid full adder , 2016, 2016 20th International Symposium on VLSI Design and Test (VDAT).

[6]  A. G. Ivakhnenko,et al.  Polynomial Theory of Complex Systems , 1971, IEEE Trans. Syst. Man Cybern..

[7]  Magdy A. Bayoumi,et al.  Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Martin Margala,et al.  Investigating the Impact of Logic and Circuit Implementation on Full Adder Performance , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[9]  Tarek Darwish,et al.  Performance analysis of low-power 1-bit CMOS full adder cells , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[10]  Vinay Kumar,et al.  Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[11]  Haomin Wu,et al.  A new design of the CMOS full adder , 1992 .

[12]  Keivan Navi,et al.  Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits , 2010, VLSI Design.

[13]  M. A. Bayoumi,et al.  A framework for fair performance evaluation of 1-bit full adder cells , 1999, 42nd Midwest Symposium on Circuits and Systems (Cat. No.99CH36356).

[14]  Rajesh A. Thakker,et al.  Improving the performance of transmission gate and hybrid CMOS Full Adders in chain and tree structure architectures , 2019, Integr..