High Level Synthesis of Synchronous Parallel Controllers

In this paper the application of Petri nets to high level synthesis of synchronous parallel controllers is presented. A formal specification of a design is given in a form of an interpreted synchronous Petri net. Behavioral properties of the controller are verified using symbolic traversal of its Petri net model. The net state-space explosion problem is managed using binary decision diagrams (BDDs). Once the Petri net specification of a controller is tested, the BDD representation of the net's state-space is used to generate a state assignment with which the controller can be synthesized. The application of the proposed methodology to the design of a MAXbus port controller for a high performance Transputer Framestore and its comparison to the alternative implementation is discussed. The experimental results clearly demonstrate the advantages of the proposed method. Further, the significant increase of the applicability of this approach has also been achieved.

[1]  Petru Eles,et al.  Synthesis of VHDL concurrent processes , 1994, EURO-DAC '94.

[2]  Tomasz Kozlowski,et al.  State assignment algorithms for parallel controller synthesis , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[3]  D. C. Hendry.  Heterogeneous Petri net methodology for the design of complex controllers , 1994 .

[4]  Erik L. Dagless,et al.  Parallel controller synthesis from a Petri net specification , 1994, EURO-DAC '94.

[5]  James Pardey,et al.  Logic synthesis of synchronous parallel controllers , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[6]  Ilan Beer,et al.  Efficient Model Checking by Automated Ordering of Transition Relation Partitions , 1994, CAV.

[7]  Jordi Cortadella,et al.  Verification of Asynchronous Circuits by BDD-based Model Checking of Petri Nets , 1995, Application and Theory of Petri Nets.

[8]  J. M. Saul,et al.  Parallel controller synthesis using Petri nets , 1995 .

[9]  Alexandre Yakovlev,et al.  Checking signal transition graph implementability by symbolic BDD traversal , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[10]  Edmund M. Clarke,et al.  Symbolic model checking for sequential circuit verification , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Olivier Coudert,et al.  Verifying Temporal Properties of Sequential Machines without Building Their State Diagrams , 1990, CAV.

[12]  Mikael Patel.  Random logic circuit implementation of extended Timed Petri Nets , 1990 .

[13]  P. R. Stephan,et al.  SIS : A System for Sequential Circuit Synthesis , 1992 .

[14]  Robert Valette,et al.  Petri nets as a common tool for design verification and hardware simulation , 1976, DAC '76.

[15]  Tadao Murata,et al.  Petri nets: Properties, analysis and applications , 1989, Proc. IEEE.

[16]  Gianfranco Balbo,et al.  Performance Issues in Parallel Programming , 1992, Application and Theory of Petri Nets.

[17]  Edmund M. Clarke,et al.  Automatic Verification of Sequential Circuits Using Temporal Logic , 1986, IEEE Transactions on Computers.

[18]  Randal E. Bryant,et al.  Efficient implementation of a BDD package , 1991, DAC '90.

[19]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[20]  Edmund M. Clarke,et al.  Sequential circuit verification using symbolic model checking , 1991, DAC '90.

[21]  Jordi Cortadella,et al.  Petri Net Analysis Using Boolean Manipulation , 1994, Application and Theory of Petri Nets.