Conflict Modelling and Instruction Scheduling in Code Generation for In-House DSP Cores

Application domain specific DSP cores are becoming increasingly popular due to their advantageous trade-off between flexibility and cost. However, existing code generation methods are hampered by the combination of tight timing and resource constraints, imposed by the throughput requirements of DSP algorithms together with a fixed core architecture. In this paper, we present a method to model resource and instruction set conflicts uniformly and statically before scheduling. With the model we exploit the combination of all possible constraints, instead of being hampered by them. The approach results in an exact and run time efficient method to solve the instruction scheduling problem, which is illustrated by real life examples.

[1]  Jochen A. G. Jess,et al.  Exact scheduling strategies based on bipartite graph matching , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[2]  Gaetano Borriello,et al.  Software Scheduling in the Co-Synthesis of Reactive Real-Time Systems , 1994, 31st Design Automation Conference.

[3]  Jochen A. G. Jess,et al.  NEAT: an object oriented high-level synthesis interface , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

[4]  Youn-Long Lin,et al.  Code generation for a DSP processor , 1994, Proceedings of 7th International Symposium on High-Level Synthesis.

[5]  A. H. Timmer,et al.  Execution interval analysis under resource constraints , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[6]  Pierre G. Paulin,et al.  CodeSyn: a retargetable code synthesis system (abstract) , 1994, ISSS '94.

[7]  N. S. Mendelsohn,et al.  Two Algorithms for Bipartite Graphs , 1963 .

[8]  T. C. May,et al.  Instruction-set matching and selection for DSP and ASIP code generation , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[9]  Peter Marwedel.  Tree-based mapping of algorithms to predefined structures , 1993, ICCAD.

[10]  Peter Marwedel,et al.  Tree-based mapping of algorithms to predefined structures , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[11]  Pierre G. Paulin,et al.  CodeSyn : A Retargetable Code Synthesis System , 1997 .

[12]  Hugo De Man,et al.  Instruction set definition and instruction selection for ASIPs , 1994, Proceedings of 7th International Symposium on High-Level Synthesis.

[13]  Jochen A. G. Jess,et al.  Execution interval analysis under resource constraints , 1993, ICCAD.

[14]  Pierre G. Paulin,et al.  Force-directed scheduling for the behavioral synthesis of ASICs , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  Jochen A. G. Jess,et al.  Efficient code generation for in-house DSP-cores , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[16]  Joos Vandewalle,et al.  Loop Optimization in Register-Transfer Scheduling for DSP-Systems , 1989, 26th ACM/IEEE Design Automation Conference.

[17]  Hugo De Man,et al.  Data routing: a paradigm for efficient data-path synthesis and code generation , 1994, Proceedings of 7th International Symposium on High-Level Synthesis.