Temperature aware energy-reliability trade-offs for mapping of throughput-constrained applications on multimedia MPSoCs

This paper proposes a design-time (offline) analysis technique to determine application task mapping and scheduling on a multiprocessor system and the voltage and frequency levels of all cores (offline DVFS) that minimize application computation and communication energy, simultaneously minimizing processor aging. The proposed technique incorporates (1) the effect of the voltage and frequency on the temperature of a core; (2) the effect of neighboring cores' voltage and frequency on the temperature (spatial effect); (3) pipelined execution and cyclic dependencies among tasks; and (4) the communication energy component which often constitutes a significant fraction of the total energy for multimedia applications. The temperature model proposed here can be easily integrated in the design space exploration for multiprocessor systems. Experiments conducted with MPEG-4 decoder on a real system demonstrate that the temperature using the proposed model is within 5% of the actual temperature clearly demonstrating its accuracy. Further, the overall optimization technique achieves 40% savings in energy consumption with 6% increase in system lifetime.

[1]  Dakai Zhu,et al.  Reliability-Aware Energy Management for Periodic Real-Time Tasks , 2007, 13th IEEE Real Time and Embedded Technology and Applications Symposium (RTAS'07).

[2]  Bharadwaj Veeravalli,et al.  Communication and migration energy aware design space exploration for multicore systems with intermittent faults , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[3]  Sander Stuijk,et al.  SDF^3: SDF For Free , 2006, Sixth International Conference on Application of Concurrency to System Design (ACSD'06).

[4]  Qiang Xu,et al.  Energy-efficient task allocation and scheduling for multi-mode MPSoCs under lifetime reliability constraint , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[5]  Lei He,et al.  Temperature and supply Voltage aware performance and power modeling at microarchitecture level , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Luca Benini,et al.  Packetized on-chip interconnect communication analysis for MPSoC , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[7]  Radu Marculescu,et al.  FARM: Fault-aware resource management in NoC-based multiprocessor platforms , 2011, 2011 Design, Automation & Test in Europe.

[8]  Petru Eles,et al.  Steady-state dynamic temperature analysis and reliability optimization for embedded multiprocessor systems , 2012, DAC Design Automation Conference 2012.

[9]  Xiaobo Sharon Hu,et al.  Temperature-Aware Scheduling and Assignment for Hard Real-Time Applications on MPSoCs , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  Radu Marculescu,et al.  Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[11]  Qiang Xu,et al.  Lifetime reliability-aware task allocation and scheduling for MPSoC platforms , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[12]  Bharadwaj Veeravalli,et al.  Reliability-driven task mapping for lifetime extension of networks-on-chip based multiprocessor systems , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[13]  Petru Eles,et al.  Scheduling and voltage scaling for energy/reliability trade-offs in fault-tolerant time-triggered embedded systems , 2007, 2007 5th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[14]  Kevin Skadron,et al.  Temperature-aware microarchitecture: Modeling and implementation , 2004, TACO.

[15]  Xiaobo Sharon Hu,et al.  Enhancing multicore reliability through wear compensation in online assignment and scheduling , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[16]  Dakai Zhu,et al.  Reliability-Aware Energy Management for Periodic Real-Time Tasks , 2009, IEEE Trans. Computers.

[17]  Yu Cao,et al.  Predictive Technology Model for Nano-CMOS Design Exploration , 2006, Nano-Net.

[18]  Sarma B. K. Vrudhula,et al.  Performance Optimal Online DVFS and Task Migration Techniques for Thermally Constrained Multi-Core Processors , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[19]  Petru Eles,et al.  Energy-efficient mapping and scheduling for DVS enabled distributed embedded systems , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[20]  Sander Stuijk,et al.  Throughput Analysis of Synchronous Data Flow Graphs , 2006, Sixth International Conference on Application of Concurrency to System Design (ACSD'06).

[21]  Tajana Simunic,et al.  Hybrid dynamic energy and thermal management in heterogeneous embedded multiprocessor SoCs , 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

[22]  E.A. Lee,et al.  Synchronous data flow , 1987, Proceedings of the IEEE.

[23]  Tajana Simunic,et al.  Temperature-aware MPSoC scheduling for reducing hot spots and gradients , 2008, 2008 Asia and South Pacific Design Automation Conference.

[24]  Lothar Thiele,et al.  Thermally optimal stop-go scheduling of task graphs with real-time constraints , 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

[25]  Donald E. Thomas,et al.  A case for lifetime-aware task mapping in embedded chip multiprocessors , 2010, 2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[26]  Pradip Bose,et al.  The case for lifetime reliability-aware microprocessors , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..