Optimal $ \Sigma \Delta$ Modulator Architectures for Fractional-$ {N}$ Frequency Synthesis

This paper presents a comparative study of ΣΔ modulators for use in fractional-N phase-locked loops. It proposes favorable modulator architectures while taking into consideration not only the quantization noise of the modulator but also other loop nonidealities such as the charge pump current mismatch that contributes to the degradation in the synthesized tone's phase noise. The proper choice of the modulator architecture is found to be dependent upon the extent of the nonideality, reference frequency, and loop bandwidth. Three modulator architectures are then proposed for low, medium, and high levels of nonidealities.

[1]  Mohammed Ismail,et al.  CMOS PLLs and VCOs for 4G Wireless , 2004 .

[2]  Nikolaus Klemmer,et al.  Enhanced phase noise modeling of fractional-N frequency synthesizers , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[3]  Juha Kostamovaara,et al.  A practical /spl Delta/-/spl Sigma/ modulator design method based on periodical behavior analysis , 2005, IEEE Transactions on Circuits and Systems II: Express Briefs.

[4]  B. Miller,et al.  A multiple modulator fractional divider , 1990, 44th Annual Symposium on Frequency Control.

[5]  Tad A. Kwasniewski,et al.  Reduced complexity, high performance digital delta-sigma modulator for fractional-N frequency synthesis , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[6]  Izzet Kale,et al.  Rigorous analysis of delta-sigma modulators for fractional-N PLL frequency synthesis , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[7]  Mitchell D. Trott,et al.  A Modeling Approach for – Fractional- N Frequency Synthesizers Allowing Straightforward Noise Analysis , 2001 .

[8]  Bram De Muer,et al.  On the analysis of ΔΣ fractional-N frequency synthesizers for high-spectral purity , 2003, IEEE Trans. Circuits Syst. II Express Briefs.

[9]  M.J. Borkowski,et al.  Post modulator filtering in /spl Delta/-/spl Sigma/ fractional-N frequency synthesis , 2004, The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04..

[10]  M. Steyaert,et al.  A CMOS monolithic ΔΣ-controlled fractional-N frequency synthesizer for DCS-1800 , 2002, IEEE J. Solid State Circuits.

[11]  Bang-Sup Song,et al.  A 1.1 GHz CMOS fractional-N frequency synthesizer with a 3b 3rd-order ΔΣ modulator , 2000 .

[12]  Huazhong Yang,et al.  An analytical phase noise model of charge pump mismatch in sigma-delta frequency synthesizer , 2006 .

[13]  H. Hedayati,et al.  Closed-Loop Nonlinear Modeling of Wideband$SigmaDelta$Fractional-$N$Frequency Synthesizers , 2006, IEEE Transactions on Microwave Theory and Techniques.

[14]  B.-S. Song,et al.  A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order /spl Delta//spl Sigma/ modulator , 2000, IEEE Journal of Solid-State Circuits.

[15]  S. Norsworthy.  Effective dithering of sigma-delta modulators , 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

[16]  F. Maloberti,et al.  A comparative study of digital /spl Sigma//spl Delta/ modulators for fractional-N synthesis , 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).

[17]  Howard C. Luong,et al.  A 1.5-V 900-MHz monolithic CMOS fast-switching frequency synthesizer for wireless applications , 2000 .

[18]  K. Suyama,et al.  Design considerations in high-order multi-bit sigma-delta modulators , 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.