A Hardwar/Software Co-design Environment for Reconfigurable Logic Systems

The design of reconfigurable systems is currently an area of intense interest within the programmable logic community. One of the main obstacles to the widespread adoption of this technology is the relative immaturity of the associated design methodologies and tools. This paper reports on a development environment and associated tools for the implementation and debugging of reconfigurable applications. These tools are part of a larger program of work to improve the construction of reconfigurable systems. The current environment is specific to a custom Xilinx XC6200 development board, but the principles are generic and portable to other reconfigurable systems and architectures.

[1]  Patrick Lysaght,et al.  Fast Reconfigurable Crossbar Switching in FPGAs , 1996, FPL.

[2]  Wayne Luk,et al.  Riley-2: A flexible platform for codesign and dynamic reconfigurable computing research , 1997, FPL.

[3]  Ahmed Amine Jerraya,et al.  Cosmos: A Transformational Co-Design Tool for Multiprocessor Architectures , 1997 .

[4]  David Robinson,et al.  Performance evaluation of a full speed PCI initiator and target subsystem using FPGAs , 1997, FPL.

[5]  Reiner W. Hartenstein,et al.  Field-Programmable Logic Smart Applications, New Paradigms and Compilers , 1996, Lecture Notes in Computer Science.

[6]  Hiroto Yasuura,et al.  Real-time task scheduling for a variable voltage processor , 1999, Proceedings 12th International Symposium on System Synthesis.

[7]  Sharad Malik,et al.  Power analysis and minimization techniques for embedded DSP software , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[8]  Luca Benini,et al.  System-level power optimization: techniques and tools , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[9]  Dirk Herrmann,et al.  The Cosyma System , 1997 .

[10]  Wayne Wolf.  Hardware/software co-synthesis algorithms , 1999 .

[11]  Joseph A. Fisher.  Customized instruction-sets for embedded processors , 1999, DAC '99.

[12]  Luciano Lavagno,et al.  Scheduling for Embedded Real-Time Systems , 1998, IEEE Des. Test Comput..

[13]  Frank Vahid,et al.  SpecSyn: an environment supporting the specify-explore-refine paradigm for hardware/software system design , 1998, IEEE Trans. Very Large Scale Integr. Syst..

[14]  Brad L. Hutchings,et al.  Design methodologies for partially reconfigured systems , 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[15]  Luca Benini,et al.  A survey of design techniques for system-level dynamic power management , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[16]  Hiroto Yasuura,et al.  Voltage scheduling problem for dynamically variable voltage processors , 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

[17]  Marilyn Wolf,et al.  An architectural co-synthesis algorithm for distributed, embedded computing systems , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[18]  Cristina Silvano,et al.  Power estimation of embedded systems: a hardware/software codesign approach , 1998, IEEE Trans. Very Large Scale Integr. Syst..

[19]  Patrick Lysaght,et al.  A simulation tool for dynamically reconfigurable field programmable gate arrays , 1996, IEEE Trans. Very Large Scale Integr. Syst..

[20]  H. De Man,et al.  CoWare—A design environment for heterogeneous hardware/software systems , 1996, Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition.

[21]  Patrick Lysaght.  Towards an expert system for a priori estimation of reconfiguration latency in dynamically reconfigurable logic , 1997, FPL.

[22]  John A. Clark,et al.  Holistic schedulability analysis for distributed hard real-time systems , 1994, Microprocess. Microprogramming.

[23]  Gustavo de Veciana,et al.  Design Challenges for New Application-Specific Processors , 2000, IEEE Des. Test Comput..

[24]  Luciano Lavagno,et al.  A case study in computer-aided co-design of embedded controllers , 1994, Des. Autom. Embed. Syst..

[25]  David Robinson,et al.  New CAD Framework Extends Simulation of Dynamically Reconfigurable Logic , 1998, FPL.

[26]  P. W. Foulk.  Data-folding in SRAM configurable FPGAs , 1993, [1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines.

[27]  Jordi Madrenas,et al.  VHDL Modeling of Fast Dynamic Reconfiguration on Novel Multicontext RAM-based Field Programmable Devices , 1997 .