Fast extraction for 3-D inductance and resistance in interconnects

With the development of VLSI circuits, the feature size has been decreased to the deep sub-micron level, and working frequency has reached 3 GHz. IC performance depends directly on parasitic interconnect inductance and resistance. In this paper, we propose a format to describe 3D hierarchical interconnects, and an approach automatically partitioning filaments in consideration of the skin effect. An improved multipole accelerative computation based on the non-uniform cube subdivision is implemented. Numerical results show that the extractor presented here runs several to more than ten times faster than the FastHenry (M. Kamon et al., IEEE Trans. on Microwave Theory and Techniques, pt. 2, pp. 1750-1758, 1994) with comparable accuracy.