Scalable event routing in hierarchical neural array architecture with global synaptic connectivity

An asynchronous communication scheme for scalable routing of spike events in large-scale neuromorphic hardware is presented. The routing scheme extends the Address-Event Representation (AER) protocol for spike event communication to a modular, hierarchical architecture supporting efficient implementation of global synaptic inter-connectivity across a cellular matrix of message parsing axonal relay nodes at varying spatial scales. This paper presents a probabilistic framework for analyzing trade-offs in throughput and latency of synaptic communication as a function of load and geometry, and simulation results verifying the statistics of traffic flow across the architecture.

[1]  Eugenio Culurciello,et al.  High dynamic range, arbitrated address event representation digital imager , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[2]  Rodney J. Douglas,et al.  A pulse-coded communications infrastructure for neuromorphic systems , 1999 .

[3]  Kwabena Boahen,et al.  Learning in Silicon: Timing is Everything , 2005, NIPS.

[4]  Bertram E. Shi,et al.  Expandable Networks for Neuromorphic Chips , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[5]  Stephen R. Deiss.  Connectionism without the connections , 1994, Proceedings of 1994 IEEE International Conference on Neural Networks (ICNN'94).

[6]  Kwabena Boahen,et al.  A throughput-on-demand address-event transmitter for neuromorphic chips , 1999, Proceedings 20th Anniversary Conference on Advanced Research in VLSI.

[7]  J. Little.  A Proof for the Queuing Formula: L = λW , 1961 .

[8]  Johannes Schemmel,et al.  Realizing biological spiking network models in a configurable wafer-scale hardware system , 2008, 2008 IEEE International Joint Conference on Neural Networks (IEEE World Congress on Computational Intelligence).

[9]  Charles E. Leiserson,et al.  Fat-trees: Universal networks for hardware-efficient supercomputing , 1985, IEEE Transactions on Computers.

[10]  Guy Pujolle,et al.  Introduction to queueing networks , 1987 .

[11]  Tobi Delbrück,et al.  CAVIAR: A 45k Neuron, 5M Synapse, 12G Connects/s AER Hardware Sensory–Processing– Learning–Actuating System for High-Speed Visual Object Recognition and Tracking , 2009, IEEE Transactions on Neural Networks.

[12]  Gert Cauwenberghs,et al.  Dynamically Reconfigurable Silicon Array of Spiking Neurons With Conductance-Based Synapses , 2007, IEEE Transactions on Neural Networks.

[13]  Luis A. Plana,et al.  SpiNNaker: Mapping neural networks onto a massively-parallel chip multiprocessor , 2008, 2008 IEEE International Joint Conference on Neural Networks (IEEE World Congress on Computational Intelligence).

[14]  Gert Cauwenberghs,et al.  Spike Timing-Dependent Plasticity in the Address Domain , 2002, NIPS.

[15]  Misha A. Mahowald,et al.  An Analog VLSI System for Stereoscopic Vision , 1994 .