Forward and inverse 2-D DCT architectures targeting HDTV for H.264/AVC video compression standard

−− This paper presents the architecture and the VHDL design of the integer TwoDimensional Discrete Cosine Transform (2-D DCT) used in the H.264/AVC codecs. The forward and inverse 2-D DCT architectures were designed and their synthesis results mapped to Altera FPGAs are presented. The 2-D DCT calculation is performed by exploring the separability property, in such way, each 2-D DCT architecture is divided in two 1-D DCT calculations that are joined through a transpose buffer. The 1-D DCT transforms implemented and herein described are multiplierless, hence optimized shift-add operations are used. The architectures have a dedicated pipeline, optimized to process one input data per clock cycle. These architectures are able to cope with H.264/AVC encoder or decoder requirements targeting High Definition Digital Television (HDTV), with 1920x1080 pixel/frame at 30 frames per second.

[1]  Thomas Wiegand,et al.  Draft ITU-T recommendation and final draft international standard of joint video specification , 2003 .

[2]  Jiun-In Guo,et al.  An efficient direct 2-D transform coding IP design for MPEG-4 AVC/H.264 , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[3]  Anastasis A. Sofokleous,et al.  Review: H.264 and MPEG-4 Video Compression: Video Coding for Next-generation Multimedia , 2005, Comput. J..

[4]  Bin-Da Liu,et al.  High throughput 2-D transform architectures for H.264 advanced video coders , 2004, The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings..

[5]  Sergio Bampi,et al.  High throughput multitransform and multiparallelism IP for H.264/AVC video compression standard , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[6]  Ajay Luthra,et al.  Overview of the H.264/AVC video coding standard , 2003, IEEE Trans. Circuits Syst. Video Technol..

[7]  Gary J. Sullivan,et al.  Video Compression - From Concepts to the H.264/AVC Standard , 2005, Proceedings of the IEEE.

[8]  Roman C. Kordasiewicz,et al.  Hardware implementation of the optimized transform and quantization blocks of H.264 , 2004, Canadian Conference on Electrical and Computer Engineering 2004 (IEEE Cat. No.04CH37513).

[9]  Jean-Michel Bergé,et al.  Circuit synthesis with VHDL , 1994 .

[10]  Henrique S. Malvar,et al.  Low-complexity transform and quantization in H.264/AVC , 2003, IEEE Trans. Circuits Syst. Video Technol..

[11]  Yücel Altunbasak,et al.  Performance comparison of the emerging H.264 video coding standard with the existing standards , 2003, 2003 International Conference on Multimedia and Expo. ICME '03. Proceedings (Cat. No.03TH8698).

[12]  Iain E. G. Richardson,et al.  H.264 and MPEG-4 Video Compression: Video Coding for Next-Generation Multimedia , 2003 .

[13]  Xuemin Chen,et al.  Video coding using the H.264/MPEG-4 AVC compression standard , 2004, Signal Process. Image Commun..

[14]  Mathias Wien,et al.  Variable block-size transforms for H.264/AVC , 2003, IEEE Trans. Circuits Syst. Video Technol..

[15]  Jar-Ferr Yang,et al.  Combined 2-D transform and quantization architectures for H.264 video coders , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[16]  Hung-Chi Fang,et al.  Parallel 4/spl times/4 2D transform and inverse transform architecture for MPEG-4 AVC/H.264 , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[17]  Ajay Luthra,et al.  The H.264/AVC Advanced Video Coding standard: overview and introduction to the fidelity range extensions , 2004, SPIE Optics + Photonics.