论文信息 - CAD tools for analysis of process variability effects in deep submicron CMOS circuits

CAD tools for analysis of process variability effects in deep submicron CMOS circuits

A special CAD toolset for process, device and circuit statistical simulation is described. Variability is introduced in the process parameter space, not in the space of parameters of the circuit components. As a result, complex dependencies and correlations between process parameters and circuit performance are taken into account in a realistic way. Application to analysis of static current consumption in deep submicron CMOS digital circuits is demonstrated.

[1] L. Balado,et al. CMOS leakage power at cell level , 2006, International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006..

[2] Marion Kee,et al. Analysis , 2004, Machine Translation.

[3] Marcel J. M. Pelgrom,et al. Matching properties of MOS transistors , 1989 .

[4] Wojciech Maly,et al. Computer-aided design for VLSI circuit manufacturability , 1990, Proc. IEEE.

[5] Wieslaw Kuzmicz,et al. Extension of inductive fault analysis to parametric faults in analog circuits with application to test generation , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

[6] C. Hu,et al. Threshold voltage model for deep-submicrometer MOSFETs , 1993 .

[7] Thomas Skotnicki. Nano-CMOS & Emerging Technologies - Myths and Hopes , 2006 .

[8] Wieslaw Kuzmicz,et al. Device and parasitic oriented circuit extractor , 1987 .

[9] Hans Jurgen Mattausch,et al. Impurity-profile-based threshold-voltage model of pocket-implanted MOSFETs for circuit simulation , 2002 .

[10] Zbigniew Jaworski,et al. Coupling a Statistical Process-Device Simulator with a Circuit Layout Extractor for a Realistic Circuit Simulation of VLSI Circuits , 1993 .

[11] Andrzej J. Strojwas,et al. Statistical Simulation of the IC Manufacturing Process , 1982, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.