Estimation of signal transition activity in FIR filters implementedby a MAC architecture

A novel method for the accurate calculation of the transition activity at the nodes of a multiplier-accumulator (MAC) architecture implementing finite impulse response filters is proposed in this paper. The method is developed for input signals, which can be described by a stationary Gaussian process. The transition activity per bit of a signal word is modeled according to the dual-bit-type (DBT) model and it is described as a function of the signal statistics. An efficient analytical method has been developed for the determination of the signal statistics at each node of the MAC architecture. It is based on the mathematical formulation of the multiplexing in time of signal sequences with known statistics. The effect of the multiplexing mechanism on the breakpoints of the DBT model, which influences significantly the accuracy of the method, is also determined. Several experiments both with synthetic and real data have been conducted. The numerical results produced by the proposed models are in very good agreement with the measured values of the transition activity.

[1]  A. Tatsaki,et al.  Accurate calculation of bit-level transition activity using word-level statistics and entropy function , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[2]  Radu Marculescu,et al.  Information theoretic measures for power analysis [logic design] , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  R. Marculescu,et al.  Information theoretic measures for power analysis : Low power design , 1996 .

[4]  Jacob A. Abraham,et al.  An easily computed functional level testability measure , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[5]  Farid N. Najm,et al.  A survey of power estimation techniques in VLSI circuits , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[6]  Anantha P. Chandrakasan,et al.  Low-power CMOS digital design , 1992 .

[7]  Naresh R. Shanbhag,et al.  Analytical estimation of transition activity for DSP architectures , 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

[8]  Naresh R. Shanbhag,et al.  Analytical estimation of signal transition activity from word-level statistics , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Jan M. Rabaey,et al.  Architectural power analysis: The dual bit type method , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[10]  Naresh R. Shanbhag,et al.  Analytical expressions for average bit statistics of signal lines in DSP architectures , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[11]  Mohamed I. Elmasry,et al.  Low-Power Digital VLSI Design: Circuits and Systems , 1995 .