Fan-Out Panel-Level Packaging of Mini-LED RGB Display

In this study, the feasibility of mini-light-emitting diode (LED) RGB display fabricated by a chip-first fan-out panel-level packaging is investigated. Emphasis is placed on the design, materials, process, fabrication, and reliability of the mini-LED RGB display package on a printed circuit board (PCB). The mini-LEDs under consideration and their sizes are red (<inline-formula> <tex-math notation="LaTeX">$125 \times 250 \times 100 ~\mu \text{m}$ </tex-math></inline-formula>), green (<inline-formula> <tex-math notation="LaTeX">$130 \times 270 \times 100 ~\mu \text{m}$ </tex-math></inline-formula>), and blue (<inline-formula> <tex-math notation="LaTeX">$130 \times 270 \times 100 ~\mu \text{m}$ </tex-math></inline-formula>). The spacing among the RGB mini-LEDs is <inline-formula> <tex-math notation="LaTeX">$80~\mu \text{m}$ </tex-math></inline-formula>, the pixel-to-pixel spacing is also <inline-formula> <tex-math notation="LaTeX">$\sim 80~\mu \text{m}$ </tex-math></inline-formula>, and the pixel pitch is <inline-formula> <tex-math notation="LaTeX">$625~\mu \text{m}$ </tex-math></inline-formula>. The temporary glass panel for making the redistribution layers (RDLs) of the package is <inline-formula> <tex-math notation="LaTeX">$515 \times 510 \times 1.1$ </tex-math></inline-formula> mm in size. To increase the SMT assembly yield on the PCB, the mini-LEDs are grouped into 4(<inline-formula> <tex-math notation="LaTeX">$2 \times 2$ </tex-math></inline-formula> pixels)-in-one surface mount device (SMD), that is, a total of 12 R, B, and G mini-LEDs. A PCB (<inline-formula> <tex-math notation="LaTeX">$132\,\,mm \times 77$ </tex-math></inline-formula> mm) is designed and fabricated for the drop test of the mini-LED package. Thermal cycling of the mini-LED SMD PCB assembly is also performed by a nonlinear temperature- and time-dependent finite-element simulation.

[1]  John H. Lau,et al.  Chip on Board: Technologies for Multichip Modules , 1995 .

[3]  B. Keser,et al.  The Redistributed Chip Package: A Breakthrough for Advanced Packaging , 2007, 2007 Proceedings 57th Electronic Components and Technology Conference.

[4]  J. Lau,et al.  Fan-Out Wafer-Level Packaging for Heterogeneous Integration , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

[5]  J. Lau Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging , 2019, Journal of Electronic Packaging.

[6]  John H. Lau,et al.  3D LED and IC wafer level packaging , 2010 .

[7]  A. Kumar,et al.  Design and development of a multi-die embedded micro wafer level package , 2008, 2008 58th Electronic Components and Technology Conference.

[8]  Seung Wook Yoon,et al.  Fanout flipchip eWLB (embedded Wafer Level Ball Grid Array) technology as 2.5D packaging solutions , 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

[9]  H. Hedler,et al.  An embedded device technology based on a molded reconfigured wafer , 2006, 56th Electronic Components and Technology Conference 2006.

[10]  Benson Lin,et al.  A Novel System in Package with Fan-Out WLP for High Speed SERDES Application , 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

[11]  J. Lau,et al.  Chip-First Fan-Out Panel-Level Packaging for Heterogeneous Integration , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

[12]  N. Lee,et al.  Assembly and Reliability of Lead-Free Solder Joints , 2020 .

[13]  Chin-Li Kao,et al.  Wafer Warpage Experiments and Simulation for Fan-Out Chip on Substrate , 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

[14]  John H. Lau,et al.  Fan-Out Wafer-Level Packaging , 2018 .