A temperature accelerated model for high state retention loss of nitride storage flash memory
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Chih-Yuan Lu | W.J. Tsai | A. Kuo | M.Y. Lee | N.K. Zous | T. Huang | T. Wang | S. Yin | Chih-Yuan Lu | N. Zous | W. Tsai | S. Yin | T. Huang | M.Y. Lee | A. Kuo | T. Wang
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Interface state creation and charge trapping in the medium-to-high gate voltage range (V/sub d//2>or=V/sub g/
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