Performance limits of CMOS ULSI

An analytic MOST model has been developed to calculate accurately threshold voltage at submicrometer dimensions and to predict the scaling limits of digital CMOS circuits. Salient results show that for 2-V power-supply voltages, channel lengths as small as 0.14 µm for static E/E CMOS, 0.26 µm for static E/D CMOS, 0.29 µm for dynamic transmission-gate CMOS, and 0.45 µm for static E/D NMOS circuits are possible. At submicrometer dimensions, CMOS offers as much as a 3:1 scaling advantage in minimum channel length which translates to a 5:1 improvement in gate delay when compared to NMOS. Thus CMOS is projected as the dominant ULSI technology, not only due to its well known large operating margins, low static-power dissipation and design flexibility but also due to markedly superior speed.

[1]  P. Solomon.  A comparison of semiconductor devices for high-speed logic , 1982 .

[2]  F. Klaassen,et al.  Device down scaling and expected circuit performance , 1979 .

[3]  J. Brews.  Subthreshold behavior of uniformly and nonuniformly doped long-channel MOSFET , 1979, IEEE Transactions on Electron Devices.

[4]  R. R. Troutman,et al.  VLSI limitations from drain-induced barrier lowering , 1979 .

[5]  W. Fichtner,et al.  Generalized guide for MOSFET miniaturization , 1980, IEEE Electron Device Letters.

[6]  K. Ratnakumar,et al.  Invited: Circuit scaling limits for ultra-large-scale integration , 1981, 1981 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[7]  Hsiao-Liang Chen,et al.  A limitation of channel length in dynamic memories , 1980, IEEE Transactions on Electron Devices.

[8]  G. Baccarani,et al.  IIA-1 generalized scaling theory and its application to a 1/4 micron mosfet design , 1982, IEEE Transactions on Electron Devices.

[9]  J. Meindl,et al.  Performance limits of NMOS and CMOS , 1984, 1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[10]  S.S. Wong,et al.  Nitrided-oxides for thin gate dielectrics in MOS devices , 1982, 1982 International Electron Devices Meeting.

[11]  J R Burns,et al.  SWITCHING RESPONSE OF COMPLEMENTARY SYMMETRY MOS TRANSISTOR LOGIC CIRCUITS , 1964 .

[12]  Y. See,et al.  Titanium disilicide self-aligned source/drain + gate technology , 1982, 1982 International Electron Devices Meeting.

[13]  Susumu Kohyama,et al.  CMOS Technologies for VLSI Circuits , 1981, 1981 Symposium on VLSI Technology. Digest of Technical Papers.

[14]  J. Meindl,et al.  Performance limits of E/D NMOS VLSI , 1980, 1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[15]  David A. Hodges.  Supply Voltage and Logic Levels for VLSI , 1981, 1981 Symposium on VLSI Technology. Digest of Technical Papers.

[16]  R.W. Keyes,et al.  Physical limits in digital electronics , 1975, Proceedings of the IEEE.

[17]  Akira Shintani,et al.  The Influence of Thermal Silicon Nitride Formation on VLSI Fabrication , 1983, 1983 Symposium on VLSI Technology. Digest of Technical Papers.

[18]  Robert W. Dutton,et al.  Nonplanar VLSI device analysis using the solution of Poisson's equation , 1980 .

[19]  N. Rovedo,et al.  A half micron MOSFET using double implanted LDD , 1982, 1982 International Electron Devices Meeting.

[20]  K. N. Ratnakumar,et al.  Short-channel MOST threshold voltage model , 1982 .

[21]  A. Broers,et al.  Resolution, overlay, and field-size for lithography systems , 1980, 1980 International Electron Devices Meeting.

[22]  N. Kawamura,et al.  Reliability of thin SiO2films showing intrinsic dielectric integrity , 1982, 1982 International Electron Devices Meeting.

[23]  F. M. Klaassen,et al.  Design and performance of micron-size devices , 1978 .

[24]  H. Masuda,et al.  Characteristics and limitation of scaled-down MOSFET's due to two-dimensional field effect , 1979, IEEE Transactions on Electron Devices.