Towards Embedded RAIDs-on-Chip

The dual effects of larger die sizes and technology scaling, combined with aggressive voltage scaling for power reduction, increase the error rates for on-chip memories. Traditional on-chip memory reliability techniques (e.g., ECC) incur significant power and performance overheads. In this paper, we propose a low-power-and-performance-overhead Embedded RAID (E-RAID) strategy and present Embedded RAIDs-on-Chip (E-RoC), a distributed dynamically managed reliable memory subsystem. E-RoC achieves reliability through redundancy by optimizing RAID-like policies tuned for on-chip distributed memories. We achieve on-chip reliability of memories through the use of Distributed Dynamic ScratchPad Allocatable Memories (DSPAMs) and their allocation policies. We exploit aggressive voltage scaling to reduce power consumption overheads due to parallel DSPAM accesses, and rely on the E-RoC manager to automatically handle any resulting voltage-scaling-induced errors. We demonstrate how E-RAIDs can further enhance the fault tolerance of traditional memory reliability approaches by designing E-RAID levels that exploit ECC. Finally, we show the power and flexibility of the E-RoC concept by showing the benefits of having a heterogeneous E-RAID levels that fit each application's needs (fault tolerance, power/energy, performance). Our experimental results on multimedia benchmarks show that E-RoC's fully distributed redundant reliable memory subsystem can reduce up to 85% in dynamic power consumption, and up to 61% lower latency due to error checks/corrections. On average, we see that our E-RAID levels converge to 100% Yield much faster than traditional ECC approaches. Moreover, E-RAID levels that exploit ECC (e.g., E-RAID ECC + 1, E-RAID RP + ECC) can guarantee 99.9% Yield at ultra low Vdd on average, where as SECDED and DECTED were able to attain 99.1% and 99.4% Yield respectively. Our E-RAID levels (detection and correction) achieved a worst case 93.9% Yield, where as the traditional ECC approaches achieved a worst case of 34.1% Yield. We observe an average of 22% dynamic power consumption increase by using traditional ECC approaches (EDC1, EDC8, SEC, SECDED, DEC, DECTED), where as we observe average savings of ECC, E-RAID TMR). We see that on average traditional ECC approaches are able to save static energy by 6.4%, where as our E-RAID approaches achieve 23.4% static energy savings. We observe that on average TMR) incur 2% higher overheads than traditional ECC approaches (EDC1, EDC8, SEC, SECDED, DEC, DECTED). We observe that for Vdd above 0.45, on average, our E-RAID levels with error correction support (SEC) incur 3% lower overheads over the more traditional SECDED/DECTED schemes. Finally, we observe that mixing …