Majority Logic

We extend graded modal logic (GML) to a logic that captures the concept of majority. We provide an axiomatization for majority logic, MJL, and sketch soundness and completeness proofs. Along the way, we must answer the question what is a majority of an infinite set? Majority spaces are introduced as a solution to this question.

[1]  Russell Tessier,et al.  BDD-based logic synthesis for LUT-based FPGAs , 2002, TODE.

[2]  Kenneth O. May,et al.  A Note on the Complete Independence of the Conditions for Simple Majority Decision , 1953 .

[3]  Robert E. Lyons,et al.  The Use of Triple-Modular Redundancy to Improve Computer Reliability , 1962, IBM J. Res. Dev..

[4]  Kit Fine,et al.  In so many possible worlds , 1972, Notre Dame J. Formal Log..

[5]  A. Tarski,et al.  Boolean Algebras with Operators. Part I , 1951 .

[6]  Jouko A. Väänänen,et al.  Generalized Quantifiers , 1997, Bull. EATCS.

[7]  G. Birkhoff,et al.  A ternary operation in distributive lattices , 1947 .

[8]  Johan van Benthem 1 GUARDS , BOUNDS , AND GENERALIZED SEMANTICS , 2005 .

[9]  M. de Rijke,et al.  A Note on Graded Modal Logic , 1996, Stud Logica.

[10]  Pavel Pudlák,et al.  On the Computational Power of Depth-2 Circuits with Threshold and Modulo Gates , 1997, Theor. Comput. Sci..

[11]  E. V. Huntington Sets of independent postulates for the algebra of logic , 1904 .

[12]  M. de Rijke,et al.  Modal Logic , 2001, Cambridge Tracts in Theoretical Computer Science.

[13]  Mark Fey,et al.  May’s Theorem with an infinite population , 2004, Soc. Choice Welf..

[14]  Michael Nicolaidis Fail-Safe Interfaces for VLSI: Theoretical Foundations and Implementation , 1998, IEEE Trans. Computers.

[15]  Nikolaos Gaitanis The Design of Totally Self-Checking TMR Fault-Tolerant Systems , 1988, IEEE Trans. Computers.

[16]  Stephan Tobies PSPACE Reasoning for Graded Modal Logics , 2001, J. Log. Comput..

[17]  Wiebe van der Hoek On the Semantics of Graded Modalities , 1992, J. Appl. Non Class. Logics.

[18]  Jouko A. Väänänen,et al.  Barwise: Abstract Model Theory and Generalized Quantifiers , 2004, Bulletin of Symbolic Logic.

[19]  Fusachika Miyata,et al.  Realization of Arbitrary Logical Functions Using Majority Elements , 1963, IEEE Trans. Electron. Comput..

[20]  Francesco Caro Graded modalities, II (canonical models) , 1988, Stud Logica.

[21]  Maarten de Rijke,et al.  Generalized quantifiers and modal logic , 1993, J. Log. Lang. Inf..

[22]  Valeria Bertacco,et al.  The disjunctive decomposition of logic functions , 1997, ICCAD 1997.

[23]  Charles E. Stroud,et al.  Testability and test generation for majority voting fault-tolerant circuits , 1993, J. Electron. Test..

[24]  Robert K. Brayton,et al.  DAG-aware AIG rewriting: a fresh look at combinational logic synthesis , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[25]  Kenneth O. May,et al.  A Set of Independent Necessary and Sufficient Conditions for Simple Majority Decision , 1952 .

[26]  P. Fishburn,et al.  Voting Procedures , 2022 .

[27]  Anthony S. Wojcik,et al.  A General, Constructive Approach to Fault-Tolerant Design Using Redundancy , 1989, IEEE Trans. Computers.

[28]  Robert K. Brayton,et al.  MIS: A Multiple-Level Logic Optimization System , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[29]  Maarten de Rijke,et al.  Counting Objects , 1995, J. Log. Comput..

[30]  L F Goble,et al.  Grades of modality , 1970 .

[31]  Yoshihiro Tohma,et al.  Decompositions of Logical Functions Using Majority Decision Elements , 1964, IEEE Trans. Electron. Comput..

[32]  Hagbae Kim,et al.  A Time Redundancy Approach to TMR Failures Using Fault-State Likelihoods , 1994, IEEE Trans. Computers.

[33]  J. Yuan,et al.  Double-edge-triggered D-flip-flops for high-speed CMOS circuits , 1991 .

[34]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[35]  Cecilia Metra,et al.  TMR voting in the presence of crosstalk faults at the voter inputs , 2004, IEEE Transactions on Reliability.

[36]  Maurizio Fattorosi-Barnaba,et al.  Graded modalities. I , 1985, Stud Logica.

[37]  John P. Fishburn A depth-decreasing heuristic for combinational logic: or how to convert a ripple-carry adder into a carry-lookahead adder or anything in-between , 1991, DAC '90.

[38]  Robert K. Brayton,et al.  Multilevel logic synthesis , 1990, Proc. IEEE.

[39]  H. S. Miller,et al.  Majority-Logic Synthesis by Geometric Methods , 1962, IRE Trans. Electron. Comput..

[40]  E. McCluskey Minimization of Boolean functions , 1956 .

[41]  Rohit Parikh Social Software , 2004, Synthese.

[42]  Cecilia Metra,et al.  Self-Checking Voter for High Speed TMR Systems , 2005, J. Electron. Test..

[43]  P. D. Tougaw,et al.  Logical devices implemented using quantum cellular automata , 1994 .

[44]  Massoud Pedram,et al.  Power minimization in IC design: principles and applications , 1996, TODE.

[45]  Yvon Savaria,et al.  Ratioed voter circuit for testing and fault-tolerance in VLSI processing arrays , 1996 .

[46]  Maciej J. Ciesielski,et al.  BDS: a BDD-based logic optimization system , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..