The 5nm and 7nm technology nodes will continue recent scaling trends and will deliver significantly smaller minimum features, standard cell areas and SRAM cell areas vs. the 10nm node. There are tremendous economic pressures to shrink each subsequent technology, though in a cost-effective and performance enhancing manner. IC manufacturers are eagerly awaiting EUV so that they can more aggressively shrink their technology than they could by using complicated MPT. The current 0.33NA EUV tools and processes also have their patterning limitations. EUV scanner lenses, scanner sources, masks and resists are all relatively immature compared to the current lithography manufacturing baseline of 193i. For example, lens aberrations are currently several times larger (as a function of wavelength) in EUV scanners than for 193i scanners. Robustly patterning 16nm L/S fully random logic metal patterns and 40nm pitch random logic rectangular contacts with 0.33NA EUV are tough challenges that will benefit from advanced OPC/RET. For example, if an IC manufacturer can push single exposure device layer resolution 10% tighter using improved ILT to avoid using DPT, there will be a significant cost and process complexity benefit to doing so. ILT is well known to have considerable benefits in finding flexible 193i mask pattern solutions to improve process window, improve 2D CD control, improve resolution in low K1 lithography regime and help to delay the introduction of DPT. However, ILT has not previously been applied to EUV lithography. In this paper, we report on new developments which extend ILT method to EUV lithography and we characterize the benefits seen vs. traditional EUV OPC/RET methods.
[1]
Thomas Klimpel,et al.
EUV pattern shift compensation strategies
,
2008,
SPIE Advanced Lithography.
[2]
Sang-Gyun Woo,et al.
Trade-off between inverse lithography mask complexity and lithographic performance
,
2009,
Photomask Japan.
[3]
Seong-Woon Choi,et al.
Hotspot fixing using ILT
,
2011,
Advanced Lithography.
[4]
Guangming Xiao,et al.
Cost effective solution using inverse lithography OPC for DRAM random contact layer
,
2017,
Advanced Lithography.
[5]
David Kim,et al.
Affordable and process window increasing full chip ILT masks
,
2010,
Photomask Technology.
[6]
Guangming Xiao,et al.
Enhancing fullchip ILT mask synthesis capability for IC manufacturability
,
2011,
Advanced Lithography.
[7]
Insung Kim,et al.
Investigation of EUV tapeout flow issues, requirements, and options for volume manufacturing
,
2011,
Advanced Lithography.