A Synthesis Approach for Coarse-Grained Antifuse-Based FPGAs

In this paper, we present a synthesis technique targeted toward coarse-grained antifuse-based field- programmable gate arrays (FPGAs). A macrologic cell, in this class of FPGAs, has multiple inputs and multiple outputs. A library of small logic cells can be generated from this macrocell and used to map the target netlist. First, we calculate the minimum number of macrologic cells required to map a given circuit by using either a dynamic programming or a linear programming technique. Given this minimum number of macrologic cells, we introduce an interconnect-aware clustering algorithm that assigns logic cells to individual macrocells so as to minimize the routing costs. Alternatively, a timing slack-driven clustering algorithm is presented where timing criticalities of nodes in a network are calculated and used to determine the final packing into the macrocells so as to minimize the number of the macrocells on the critical paths. When compared to results from a commercial tool, our two synthesis techniques reduce the number of macrologic cells by 12% and the maximum depth by 35%, respectively.

[1]  Giovanni De Micheli,et al.  Technology mapping for electrically programmable gate arrays , 1991, 28th ACM/IEEE Design Automation Conference.

[2]  Jonathan Rose,et al.  CALL FOR ARTICLES IEEE Design & Test of Computers Special Issue on Microprocessors , 1996 .

[3]  Vaughn Betz,et al.  VPR: A new packing, placement and routing tool for FPGA research , 1997, FPL.

[4]  Jason Cong,et al.  RASP: A General Logic Synthesis System for SRAM-Based FPGAs , 1996, Fourth International ACM Symposium on Field-Programmable Gate Arrays.

[6]  M. Pedram,et al.  Clustering techniques for coarse-grained, antifuse FPGAs , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[7]  Elias Ahmed,et al.  THE EFFECT OF LOGIC BLOCK GRANULARITY ON DEEP-SUBMICRON FPGA PERFORMANCE AND DENSITY , 2001 .

[8]  Vaughn Betz,et al.  Cluster-based logic blocks for FPGAs: area-efficiency vs. input sharing and size , 1997, Proceedings of CICC 97 - Custom Integrated Circuits Conference.

[9]  Jason Cong,et al.  FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Massoud Pedram,et al.  Boolean matching using binary decision diagrams with applications to logic synthesis and verification , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[11]  William E. Donath,et al.  Placement and average interconnection lengths of computer logic , 1979 .

[12]  Luca Benini,et al.  A survey of Boolean matching techniques for library binding , 1997, TODE.

[13]  Majid Sarrafzadeh,et al.  Dragon2000: standard-cell placement tool for large industry circuits , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[14]  Vaughn Betz,et al.  Architecture and CAD for Deep-Submicron FPGAS , 1999, The Springer International Series in Engineering and Computer Science.

[15]  Malgorzata Marek-Sadowska,et al.  Efficient circuit clustering for area and power reduction in FPGAs , 2002, FPGA '02.

[16]  Stephen D. Brown,et al.  Architecture of FPGAs and CPLDs: A Tutorial , 2000 .

[17]  Guy Lemieux,et al.  Logic block clustering of large designs for channel-width constrained FPGAs , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[18]  Vaughn Betz,et al.  Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density , 1999, FPGA '99.

[19]  Massoud Pedram,et al.  Technology mapping and packing for coarse-grained, anti-fuse based FPGAs , 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

[20]  Jason Cong,et al.  Combinational logic synthesis for LUT based field programmable gate arrays , 1996, TODE.

[21]  M. Sarrafzadeh,et al.  RPack: routability-driven packing for cluster-based FPGAs , 2001, Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455).

[22]  Massoud Pedram,et al.  Technology mapping and packing for coarse-grained, anti-fuse based FPGAs , 2004 .

[23]  Majid Sarrafzadeh,et al.  RPack: routability-driven packing for cluster-based FPGAs , 2001, ASP-DAC '01.

[24]  P. R. Stephan,et al.  SIS : A System for Sequential Circuit Synthesis , 1992 .