VLSI Design of a Hardware Efficient FFT Processor

This paper presents a CORDIC-based radix-4 FFT processor, which adopts an improved conflict-free parallel memory access scheme and the pipelined CORDIC architecture. By generating the twiddle factor correctly, the proposed FFT processor eliminates the need of ROM making it memory-efficient. Synthesis results show that the 16-bit 1024-point FFT processor only has 45 K equivalent gates with area of 0.13 mm2 excluding memories in Chartered 90 nm CMOS technology. When the operating frequency is 350 MHz, the proposed FFT processor performs 1024-point FFT every 3.94 μs.

[1]  Tze-Yun Sung.  Memory-efficient and high-speed split-radix FFT/IFFT processor based on pipelined CORDIC rotations , 2006 .

[2]  Yingning Peng,et al.  Pipeline FFT Architectures Optimized for FPGAs , 2009, Int. J. Reconfigurable Comput..

[3]  Keshab K. Parhi,et al.  A Pipelined FFT Architecture for Real-Valued Signals , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[4]  David Blaauw,et al.  Energy-optimized high performance FFT processor , 2011, 2011 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).

[5]  Erdal Oruklu,et al.  Reduced Memory and Low Power Architectures for CORDIC-based FFT Processors , 2012, J. Signal Process. Syst..

[6]  Jack E. Volder.  The CORDIC Trigonometric Computing Technique , 1959, IRE Trans. Electron. Comput..

[7]  Jarmo Takala,et al.  Conflict-free parallel memory access scheme for FFT processors , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[8]  Erdal Oruklu,et al.  An Efficient FFT Engine With Reduced Addressing Logic , 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.

[9]  Tom E. Bishop,et al.  Blind Image Restoration Using a Block-Stationary Signal Model , 2006, 2006 IEEE International Conference on Acoustics Speech and Signal Processing Proceedings.

[10]  Qihui Zhang,et al.  A Low Area Pipelined FFT Processor for OFDM-Based Systems , 2009, 2009 5th International Conference on Wireless Communications, Networking and Mobile Computing.

[11]  Jarmo Takala,et al.  Low-Power Application-Specific Processor for FFT Computations , 2011, J. Signal Process. Syst..

[12]  Ray Andraka,et al.  A survey of CORDIC algorithms for FPGA based computers , 1998, FPGA '98.

[13]  Erdal Oruklu,et al.  Reduced memory architecture for CORDIC-based FFT , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

[14]  An-Yeu Wu,et al.  VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-Based Communication Systems , 2003, EURASIP J. Adv. Signal Process..

[15]  Erdal Oruklu,et al.  Fast memory addressing scheme for radix-4 FFT implementation , 2009, 2009 IEEE International Conference on Electro/Information Technology.

[16]  Hsi-Chin Hsin,et al.  Low-power and high-speed CORDIC-based split-radix FFT processor for OFDM systems , 2010, Digit. Signal Process..