Discrete-time Decimation filter Design for Multistandard RF Sub-sampling Receiver

Sampling-based downconversion architecture was proposed in (R. Barrak et al., 2007) for multistandard RF subsampling receiver. By an appropriate choice of RF and IF subsampling frequencies complete multistandard RF bands are downconverted to baseband. This paper presents a reconfigurable discrete-time switched capacitor filter at the baseband stage which serves as an anti-aliasing and a decimation filter for analogue to digital converter. The proposed decimation filter structure consists of two cascaded second order decimation filters which are adapted respectively for GSM, UMTS and IEEE-802.11g multistandard radio receiver. The overall transfer function of this structure can be changed by switching the received channel path and adjusting the clock signal frequency controlling the switched-capacitors. IIR and FIR filter switched-capacitor implementations are also investigated to evaluate designed filter complexity and performance.

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