Thermal distribution during destructive pulses in ESD protection devices using a single-shot two-dimensional interferometric method

Thermal distribution during single destructive electrostatic discharge (ESD) events is investigated in smart power ESD protection devices using a two-dimensional holographic interferometry technique. The hot spot dynamics and the position of destructive current filaments is correlated with the thermal distribution under the nondestructive conditions and with the failure analysis results.

[1]  Wolfgang Wilkening,et al.  Pulsed thermal characterization of a reverse biased pn-junction for ESD HBM simulation , 1996 .

[2]  H. Ahmed,et al.  INFRARED ABSORPTION IN SILICON AT ELEVATED TEMPERATURES , 1996 .

[3]  D. Wunsch,et al.  Determination of Threshold Failure Levels of Semiconductor Diodes and Transistors Due to Pulse Voltages , 1968 .

[4]  C. Vest.  Holographic Interferometry , 1979 .

[5]  Kartikeya Mayaram,et al.  Self-heating effects in basic semiconductor structures , 1993 .

[6]  D. S. Campbell,et al.  Thermal failure in semiconductor devices , 1990 .

[7]  D. H. Pontius,et al.  Second breakdown and damage in junction devices , 1973 .

[8]  Dionyz Pogany,et al.  Thermal and free carrier concentration mapping during ESD event in smart Power ESD protection devices using an improved laser interferometric technique , 2000 .

[9]  A. Amerasekera,et al.  Electrothermal behavior of deep submicron nMOS transistors under high current snapback (ESD/EOS) conditions , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

[10]  B. J. Baliga,et al.  Modern Power Devices , 1987 .

[11]  M. Stecher,et al.  Interferometric temperature mapping during ESD stress and failure analysis of smart power technology ESD protection devices , 1999, Electrical Overstress/Electrostatic Discharge Symposium Proceedings. 1999 (IEEE Cat. No.99TH8396).

[12]  V. Dubec,et al.  Single-shot thermal energy mapping of semiconductor devices with the nanosecond resolution using holographic interferometry , 2002, IEEE Electron Device Letters.

[13]  V. Dubec,et al.  Investigation of ESD protection elements under high current stress in CDM-like time domain using backside laser interferometry , 2002, 2002 Electrical Overstress/Electrostatic Discharge Symposium.

[14]  G. Groos,et al.  Study of trigger instabilities in smart power technology ESD protection devices using a laser interferometric thermal mapping technique , 2001, 2001 Electrical Overstress/Electrostatic Discharge Symposium.

[15]  Dionyz Pogany,et al.  Simulation and experimental study of temperature distribution during ESD stress in smart-power technology ESD protection structures , 2000, 2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059).

[16]  G. Reimbold,et al.  An attempt to explain thermally induced soft failures during low level ESD stresses: study of the differences between soft and hard NMOS failures , 1998 .

[17]  Sergey Bychikhin,et al.  Quantitative internal thermal energy mapping of semiconductor devices under short current stress using backside laser interferometry , 2002 .