A 3.3 V-only 16 Mb DINOR flash memory
暂无分享,去创建一个
Tsutomu Yoshihara | Yasushi Terada | Yoshikazu Miyawaki | Natsuo Ajika | Atsushi Ohba | Masahiro Hatanaka | Yuichi Kunori | Masaaki Mihara | Tomoshi Futatsuya | Hirokazu Miyoshi | K. Yuzuriha | Akira Hosogane | Shinichi Kobayashi | Motoharu Ishii | Y. Uji | A. Matsuo | Y. Taniguchi | Y. Kiguchi
[1] M. Hatanaka,et al. Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory , 1993, Symposium 1993 on VLSI Circuits.
[2] N. Ajika,et al. A novel cell structure suitable for a 3 volt operation, sector erase flash memory , 1992, 1992 International Technical Digest on Electron Devices Meeting.
[3] S. Yamada,et al. A 5-V-only operation 0.6- mu m flash EEPROM with row decoder scheme in triple-well structure , 1992 .