Synthesized transparent BIST for detecting scrambled pattern-sensitive faults in RAMs

This paper describes a synthesizable, transparent, built-in self-test (BIST) scheme for random-access memories (RAMs). By altering only two parameters in a VHDL specification, BIST circuits can be automatically generated to detect 2-, 3- or 4-cell write-triggered coupling faults as well as two different classes of 5-cell faults. The 5-cell faults represent either unlinked scrambled active physical neighborhood pattern-sensitive faults (PNPSFs), or arbitrary combinations of unlinked scrambled active, static, and passive PNPSFs. The BIST scheme uses a modified version of Nicolaidis' method to make the applied tests transparent; thus the data that were held in the RAM at the start of the test will be restored by the end of the test, if no faults are present. All single faults of the above fault types, as well as most other standard fault types, are guaranteed to be detected because of the use of an aliasing-free signature analyzer. By comparing numerous intermediate signatures, the new design has a very low probability of aliasing when multiple faults are present.

[1]  Kozo Kinoshita,et al.  Test Pattern Generation for API Faults in RAM , 1985, IEEE Transactions on Computers.

[2]  Gadiel Seroussi,et al.  Vector sets for exhaustive testing of logic circuits , 1988, IEEE Trans. Inf. Theory.

[3]  Michael Nicolaidis,et al.  TRANSPARENT BIST FOR RAMS , 1992, Proceedings International Test Conference 1992.

[4]  Bruce F. Cockburn,et al.  A transparent built-in self-test scheme for detecting single V-coupling faults in RAMs , 1994, Proceedings of IEEE International Workshop on Memory Technology, Design, and Test.

[5]  Kewal K. Saluja,et al.  AN ALGORITHM TO TEST RAMS FOR PHYSICAL NEIGHBORHOOD PATTERN SENSITIVE FAULTS , 1991, 1991, Proceedings. International Test Conference.

[6]  Donald T. Tang,et al.  Iterative Exhaustive Pattern Generation for Logic Testing , 1984, IBM J. Res. Dev..

[7]  Michael Nicolaidis,et al.  Aliasing-free signature analysis for RAM BIST , 1994, Proceedings., International Test Conference.

[8]  Bruce F. Cockburn.  Tutorial on semiconductor memory testing , 1994, J. Electron. Test..

[9]  Kewal K. Saluja,et al.  An algorithm to test reconfigured RAMs , 1994, Proceedings of 7th International Conference on VLSI Design.

[10]  Sudhakar M. Reddy,et al.  Test Procedures for a Class of Pattern-Sensitive Faults in Semiconductor Random-Access Memories , 1980, IEEE Transactions on Computers.

[11]  Bruce F. Cockburn.  Deterministic tests for detecting singleV-coupling faults in RAMs , 1994, J. Electron. Test..

[12]  Mark G. Karpovsky,et al.  Transparent memory testing for pattern sensitive faults , 1994, Proceedings., International Test Conference.

[13]  Bruce F. Cockburn.  A 20 MHz test vector generator for producing tests that detect single 4- and 5-coupling faults in RAMs , 1993, Records of the 1993 IEEE International Workshop on Memory Testing.

[14]  Jacob A. Abraham,et al.  Efficient Algorithms for Testing Semiconductor Random-Access Memories , 1978, IEEE Transactions on Computers.

[15]  Frans P. M. Beenker,et al.  A realistic self-test machine for static random access memories , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[16]  Bruce F. Cockburn.  Deterministic tests for detecting scrambled pattern-sensitive faults in RAMs , 1995, Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing.