Digital signal processors that can handle 1 MHz bunch rate BPM signal processing is under development for SHINE. Two different processors have been developed at the same time, including an intermediate frequency signal processor with a sampling rate higher than 500 MHz, which can be used in general BPM applications; and a direct RF sampling processor, which can directly sample the C band cavity BPM signal without analog down-conversion modules and greatly simplifies the cavity BPM system. This paper will introduce the design, development status and performance evaluations of the processors. INTRODUCTION Shanghai HIgh repetitioN rate XFEL and Extreme light facility (SHINE) is a 3 km long hard X-ray FEL facility under construction in Shanghai. The designed beam repetition rate is 1 MHz. There are three types of BPMs locate at different sections of the machine, including stripline BPMs at injector and the gaps between superconducting accelerator sections, cold button BPMs in superconducting accelerator modules, and cavity BPMs in distributors and FEL sections. The required BPM system resolution is 10 μm, 50 μm and 200 nm at 100 pC respectively. SHINE’s BPM electronics include separate RF front-end modules and digital signal processors. Different RF frontend modules will be designed to meet the signal characteristics requirements of different BPM types, but all BPMs will use the same digital signal processors. The processor mainly contains ADCs for sampling, FPGA for signal processing and ARM for system control and communication. Considering the beam dynamic range, the relative resolution of the processor should be better than 0.1%. The processor is designed as a 1 U height standalone instrument. With advances in electronic technology, today’s FPGAs not only contain richer logic resources and faster data links, but also integrate hard ARM cores on the chip. This makes the FPGA a fully functional digital signal processing platform and makes it easier to design standalone instruments. At the same time, ADCs with sampling rate higher than 500 MHz and resolution higher than 12 bits are becoming more widely used. The high-speed serial interface JESD204B with data rates of up to 12.5 Gbps makes high-density data transmission between ADC and FPGA possible. The ADCs and FPGA are located on two PCB boards and are connected via FMC connector. Except for the basic data acquisition (DAQ) function, the processor contains another FMC connector for a WRN timing board, SFPs for fast data transmission, DDR for large amount data capture and interlock output. The processor will run Linux OS and integrate EPICS IOC for data communication. In recent years, direct RF sampling ADCs whose bandwidth greater than 6 GHz, sampling rate higher than 1.5 GHz, and resolution greater than 12 bits have begun to appear. It is mainly used for receivers in radar systems and communications and is ideal for direct sampling of C band cavity BPM signals. The RF-sampling processor can digitize RF signals directly without converting analog frequency to a lower intermediate frequency. Systems with direct RF sampling ADCs no longer require LO synthesizers, mixers, IF amplifiers, and IF filters for a typical superheterodyne receiver, reducing RF noise components, costs, design complexity, receive size, weight, and power, while improving the software programmability and flexibility of the system [1]. A direct RF sampling processor is also being developed to explorer the application of direct RF sampling technology in cavity BPM signal processing. Therefore, two types of processors are designed for SHINE, intermediate-frequency (IF) processor and directRF sampling (RF) processor. Table 1 lists the specifications of the processors to be developed. Table 1: DBPM Specifications Parameter Value