Development of 3D silicon module with TSV for system in packaging

Portable electronic products demand multifunctional module comprising digital, RF and memory functions. Through-silicon via technology provides a means of implementing complex, multi-functional integration with a higher packing density for a System in Package. A 3D silicon module with through silicon via has been developed in this work. Thermo-mechanical analysis has been performed and through silicon via interconnect design is optimized. Multiple chips representing different functional circuits are assembled using wirebond and flip chip interconnection methods. Silicon carrier is fabricated using via-first approach, the burrier copper via is exposed by special backgrinding process. A two-stack silicon module is developed and characterized in this work. Power distribution design for the silicon carrier suitable for 5 GHz digital application is studied and characterized. The module reliability has been evaluated under temperature cycling (- 40/125degC) and drop test. Samples with over-mold and underfill passed the JEDEC drop test of 1500 G & 0.5 ms pulse duration. Thermal cycle test results showed no solder joint failure.

[1]  N. Khan,et al.  Development of 3D stack package using silicon interposer for high power application , 2006, 56th Electronic Components and Technology Conference 2006.

[2]  Yuji Yano,et al.  Three-dimensional very thin stacked packaging technology for SiP , 2002, 52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345).

[3]  Seung Wook Yoon,et al.  Development of 3-D Stack Package Using Silicon Interposer for High-Power Application , 2008, IEEE Transactions on Advanced Packaging.

[4]  V. Kripesh,et al.  High performance embedded RF passive device process integration , 2008, 2008 58th Electronic Components and Technology Conference.

[5]  Keith A. Jenkins,et al.  Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection , 2005, IBM J. Res. Dev..

[6]  C. Val.  3-D packaging-applications of vertical multichip modules (MCM-V) for microsystems , 1994, Proceedings of 16th IEEE/CPMT International Electronic Manufacturing Technology Symposium.

[7]  Seung Wook Yoon,et al.  Reliability studies of a through via silicon stacked module for 3D microsystem packaging , 2006, 56th Electronic Components and Technology Conference 2006.

[8]  Said F. Al-Sarawi,et al.  A Review of 3-D Packaging Technology , 1998 .