Merging of Test Cubes using Test Point Insertion for Low-Power Test Compaction
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[1] Irith Pomeranz. Augmenting Functional Broadside Tests for Transition Fault Coverage with Bounded Switching Activity , 2011, 2011 IEEE 17th Pacific Rim International Symposium on Dependable Computing.
[2] Irith Pomeranz. Scan Shift Power of Functional Broadside Tests , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[3] Kuen-Jong Lee,et al. Test power reduction with multiple capture orders , 2004, 13th Asian Test Symposium.
[4] Jia-Guang Sun,et al. A cost-effective scan architecture for scan testing with non-scan test power and test application cost , 2003, DAC '03.
[5] Lee Whetsel,et al. Adapting scan architectures for low power operation , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).
[6] Irith Pomeranz. Signal-Transition Patterns of Functional Broadside Tests , 2013, IEEE Transactions on Computers.
[7] V. Kamakoti,et al. On Power-profiling and Pattern Generation for Power-safe Scan Tests , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.
[8] Kuen-Jong Lee,et al. Peak-power reduction for multiple-scan circuits during test application , 2000, Proceedings of the Ninth Asian Test Symposium.
[9] Irith Pomeranz. Functional Broadside Templates for Low-Power Test Generation , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[10] Irith Pomeranz,et al. Techniques for minimizing power dissipation in scan and combinational circuits during test application , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[11] Krishnendu Chakrabarty,et al. Reduction of SOC test data volume, scan power and testing time using alternating run-length codes , 2002, DAC '02.
[12] Vishwani D. Agrawal,et al. Scheduling tests for VLSI systems under power constraints , 1997, IEEE Trans. Very Large Scale Integr. Syst..
[13] Nur A. Touba,et al. Survey of Test Vector Compression Techniques , 2006, IEEE Design & Test of Computers.
[14] Kohei Miyase,et al. Test vector modification for power reduction during scan testing , 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).
[15] Sandeep K. Gupta,et al. ATPG for heat dissipation minimization during test application , 1994, Proceedings., International Test Conference.
[16] Nur A. Touba,et al. Static compaction techniques to control scan vector power dissipation , 2000, Proceedings 18th IEEE VLSI Test Symposium.