Component refinement and CSC-solving for STG decomposition

STGs (Signal Transition Graphs) give a formalism for the description of asynchronous circuits based on Petri nets. To overcome the state explosion problem one may encounter during circuit synthesis, a nondeterministic algorithm for decomposing STGs was suggested by Chu and improved by one of the present authors. Here we study how CSC-solving-which is essential for circuit synthesis-can be combined with decomposition. For this purpose, the correctness definition for decomposition is enhanced with internal signals and hierarchical decomposition is proven correct. Based on this, it is shown that speed-independent CSC-solving preserves correctness and can be combined with decomposition. Furthermore, we use our new correctness definition to give the first correctness proof for the decomposition method of Carmona and Cortadella. Finally, we compare three different implementation relations for STGs: one derived from our correctness definition; one defined by Dill based on trace structures; and one derived from I/O-compatibility defined by Carmona and Cortadella.

[1]  Josep Carmona,et al.  Input/Output Compatibility of Reactive Systems , 2002, FMCAD.

[2]  Josep Carmona.  Structural methods for the synthesis of well-formed concurrent specifications , 2003 .

[3]  Chris J. Myers,et al.  Synthesis of speed independent circuits based on decomposition , 2004, 10th International Symposium on Asynchronous Circuits and Systems, 2004. Proceedings..

[4]  Robin Milner,et al.  Communication and concurrency , 1989, PHI Series in computer science.

[5]  Tam-Anh Chu,et al.  Synthesis of self-timed VLSI circuits from graph-theoretic specifications , 1987 .

[6]  Luciano Lavagno,et al.  Logic Synthesis for Asynchronous Controllers and Interfaces , 2002 .

[7]  Raymond Cuninghame-Greene.  Proceedings of an International Symposium on the Theory of Switching , 1962 .

[8]  Walter Vogler,et al.  Improved Decomposition of Signal Transition Graphs , 2007, Fundam. Informaticae.

[9]  David L. Dill,et al.  Trace theory for automatic hierarchical verification of speed-independent circuits , 1989, ACM distinguished dissertations.

[10]  Josep Carmona,et al.  ILP Models for the Synthesis of Asynchronous Control Circuits , 2003, ICCAD.

[11]  Alex Kondratyev,et al.  Synthesis Method in Self-Timed Design Decompositional Approach , 1993 .

[12]  Walter Vogler,et al.  Decomposition in Asynchronous Circuit Design , 2002, Concurrency and Hardware Design.

[13]  Walter Vogler,et al.  Strategies for Optimised STG Decomposition , 2006, Sixth International Conference on Application of Concurrency to System Design (ACSD'06).

[14]  Luciano Lavagno,et al.  On the models for asynchronous circuit behaviour with OR causality , 1996, Formal Methods Syst. Des..

[15]  Maciej Koutny,et al.  Logic synthesis for asynchronous circuits based on Petri net unfoldings and incremental SAT , 2004, Proceedings. Fourth International Conference on Application of Concurrency to System Design, 2004. ACSD 2004..

[16]  Luciano Lavagno,et al.  Petrify: A Tool for Manipulating Concurrent Specifications and Synthesis of Asynchronous Controllers (Special Issue on Asynchronous Circuit and System Design) , 1997 .

[17]  Jo C. Ebergen,et al.  Arbiters: An Exercise in Specifying and Decomposing Asynchronously Communicating Components , 1992, Sci. Comput. Program..