论文信息 - Power aware design for next generation's Many Cores computing platforms

Power aware design for next generation's Many Cores computing platforms

We describe a comprehensive set of design techniques, applicable at different levels of abstraction that have proven to bring great potential for power optimization in industrial embedded Multi-Processing platforms.

Roberto Zafalon

[1] Saibal Mukhopadhyay,et al. Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits , 2003, Proc. IEEE.

[2] David Z. Pan,et al. Sleep transistor sizing using timing criticality and temporal currents , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[3] Margaret Martonosi,et al. Cache decay: exploiting generational behavior to reduce cache leakage power , 2001, ISCA 2001.

[4] Krishnan Srinivasan,et al. Application Specific Network-on-Chip Design with Guaranteed Quality Approximation Algorithms , 2007, 2007 Asia and South Pacific Design Automation Conference.

[5] Luca Benini,et al. Memory design techniques for low energy embedded systems , 2002 .

[6] Luca Benini,et al. An efficient profile-based algorithm for scratchpad memory partitioning , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7] Massoud Pedram,et al. Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits , 2005, IEICE Trans. Electron..

[8] Luca Benini,et al. Lightweight barrier-based parallelization support for non-cache-coherent MPSoC platforms , 2007, CASES '07.

[9] Nicola Concer,et al. aEqualized: A novel routing algorithm for the Spidergon Network On Chip , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.