SOI CMOS Technology
暂无分享,去创建一个
[1] René A. J. Janssen,et al. Electrochemical Society Proceedings , 2000 .
[2] C. Hu,et al. A 20 nm gate-length ultra-thin body p-MOSFET with silicide source/drain , 2000 .
[3] T. Stanley. Revenue potential from SOI production , 1992, 1992 IEEE International SOI Conference.
[4] D. Hui,et al. Electrostatic discharge (ESD) protection in silicon-on-insulator (SOI) CMOS technology with aluminum and copper interconnects in advanced microprocessor semiconductor chips , 1999, Electrical Overstress/Electrostatic Discharge Symposium Proceedings. 1999 (IEEE Cat. No.99TH8396).
[5] Y. Akasaka,et al. Self-aligned silicide technology for ultra-thin SIMOX MOSFETs , 1992 .
[6] Study of gate oxide leakage and charge trapping in ZMR and SIMOX SOI MOSFETs , 1988, IEEE Electron Device Letters.
[7] Tsu-Jae King,et al. Tunable work function molybdenum gate technology for FDSOI-CMOS , 2002, Digest. International Electron Devices Meeting,.
[8] V. Trivedi,et al. Scaling fully depleted SOI CMOS , 2003 .
[9] J.S.T. Huang,et al. Modeling of output snapback characteristics in n-channel SOI MOSFETs , 1992 .
[10] Heiner Ryssel,et al. Essderc '89/ 19th European Solid State Device Research Conference, Berlin , 1989 .
[11] N. K. Annamalai,et al. Leakage currents in SOI MOSFETs , 1988 .
[12] Yasuhisa Omura,et al. Simplified analysis of body-contact effect for MOSFET/SOI , 1988 .
[13] Reduction of threshold voltage at the SOI MOSFET sidewalls due to charge sharing with the front and back interfaces , 1988, Proceedings. SOS/SOI Technology Workshop.
[14] S.J. Fonash,et al. Hydrogen permeation, Si defect generation, and their interaction during CHF/sub 3//O/sub 2/ contact etching , 1994, IEEE Electron Device Letters.
[15] Sorin Cristoloveanu,et al. Narrow-channel effects and their impact on the static and floating-body characteristics of STI- and LOCOS-isolated SOI MOSFETs , 2002 .
[16] T. Ohno,et al. Fully depleted 20-nm SOI CMOSFETs with W-clad gate/source/drain layers , 2001 .
[17] C. Petersson,et al. Work function of boron-doped polycrystalline Si/sub x/Ge/sub 1-x/ films , 1997, IEEE Electron Device Letters.
[18] Emmanuel Dubois,et al. Low Schottky barrier source/drain for advanced MOS architecture: device design and material considerations , 2002 .
[19] O. Faynot,et al. High performance ultrathin SOI MOSFET's obtained by localized oxidation , 1994, IEEE Electron Device Letters.
[20] Detailed characterization and analysis of the breakdown voltage in fully depleted SOI n-MOSFET's , 1994 .
[21] N. Hirashita,et al. Fully-depleted SOI CMOSFETs with the fully-silicided source/drain structure , 2002 .
[22] Denis Flandre,et al. Influence of device engineering on the analog and RF performances of SOI MOSFETs , 2003 .
[23] Peter W. Wyatt,et al. Thin silicide development for fully-depleted SOI CMOS technology , 1998 .
[24] R. B. Marcus,et al. The Oxidation of Shaped Silicon Surfaces , 1982 .
[25] J.E. Chung,et al. Reduction of threshold voltage sensitivity in SOI MOSFET's , 1995, IEEE Electron Device Letters.
[26] Hong Shick Min,et al. An anomalous device degradation of SOI narrow width devices caused by STI edge influence , 2002 .
[27] Y. Tsunashima,et al. Dynamic threshold voltage damascene metal gate MOSFET (DT-DMG-MOS) technology for very low voltage operation of under 0.7 V , 2002 .
[28] Hyun-Kyu Yu,et al. A physical model of floating body thin film silicon-on-insulator nMOSFET with parasitic bipolar transistor , 1994 .
[29] Tadahiro Ohmi,et al. Tantalum-gate thin-film SOI nMOS and pMOS for low-power applications , 1997 .
[30] Mark S. Lundstrom,et al. A computational study of thin-body, double-gate, Schottky barrier MOSFETs , 2002 .
[31] P. Smeys,et al. Correlation between spectroscopic reflectrometry and electrical measurements of SIMOX SOI film thickness , 1992, ESSDERC '92: 22nd European Solid State Device Research conference.
[32] Denis Flandre,et al. Analog performance and application of graded-channel fully depleted SOI MOSFETs , 2000 .
[33] G. Groeseneken,et al. Double snapback in SOI nMOSFETs and its application for SOI ESD protection , 1993, IEEE Electron Device Letters.
[34] T. Tsuchiya,et al. Experimental 0.25-/spl mu/m-gate fully depleted CMOS/SIMOX process using a new two-step LOCOS isolation technique , 1995 .
[35] J. Conner,et al. Fully-depleted SOI devices with TaSiN gate, HfO2 gate dielectric, and elevated source/drain extensions , 2003, IEEE Electron Device Letters.
[36] M. Jagadesh Kumar,et al. A new lateral PNM Schottky collector bipolar transistor (SCBT) on SOI for nonsaturating VLSI logic design , 2002 .
[37] Chenming Hu,et al. SOI/bulk hybrid technology on SIMOX wafers for high performance circuits with good ESD immunity , 1995, IEEE Electron Device Letters.
[38] Jean-Pierre Colinge,et al. Improved LOCOS isolation for thin-film SOI MOSFETs , 1996 .
[39] J. McVittie,et al. Plasma Charging Damage: An Overview , 1996, Proceedings of 1st International Symposium on Plasma Process-Induced Damage.
[40] T. Hiramoto,et al. Experimental evidence for quantum mechanical narrow channel effect in ultra-narrow MOSFET's , 2000, IEEE Electron Device Letters.
[41] W. Greene,et al. 0.18-μm fully-depleted silicon-on-insulator MOSFET's , 1997, IEEE Electron Device Letters.
[42] P. Karulkar. Quality of gate oxides grown on state-of-the-art SIMOX and ZMR SOI substrates , 1993, IEEE Electron Device Letters.
[43] Jeremy C. Smith. ESD protection in thin film silicon on insulator technologies , 1998 .
[44] M. Tomizawa,et al. Design considerations for thin-film SOI/CMOS device structures , 1989 .
[45] Herman Maes,et al. The ESD protection mechanisms and the related failure modes and mechanisms observed in SOI snapback nMOSFET's , 1995 .