A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-Tap Decision Feedback Equalizer in 28 nm CMOS

This paper presents a 28 Gb/s multistandard SerDes macro which is fabricated in TSMC 28 nm CMOS process. The transimpedance amplifier (TIA) base analog front-end achieved 15 dB high-frequency boost with an on-chip compact passive inductor. The adaptation loop for the boost is decoupled from the decision feedback equalizer (DFE) adaptation by the use of a group delay algorithm. The DFE is a half-rate 1-tap unrolled design with only two total error latches for power and area reduction. A two-stage sense amplifier-based latch achieved sensitivity of 15 mV. The high-speed clock buffer uses a PMOS active inductor circuit with common-mode feedback to optimize the circuit performance. The transceiver achieves error-free operation at 28 Gbps with 34 dB channel loss, consumes the worst case power of 560 mW/lane, and fully complies with multiple standards and applications.

[1]  Pervez M. Aziz,et al.  Analysis of a class of decimated clock/data recovery architectures for serial links , 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

[2]  Pervez M. Aziz,et al.  Adaptation algorithms for a class of continuous time analog equalizers with application to serial links , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

[3]  R. G. Meyer,et al.  A wide-band low-noise monolithic transimpedance amplifier , 1986 .

[4]  Aliazam Abbasfar,et al.  A 12.5Gb/s active-inductor based transmitter for I/O applications , 2011, 2011 20th European Conference on Circuit Theory and Design (ECCTD).

[5]  Shen-Iuan Liu,et al.  A 1V 4.2mW fully integrated 2.5Gb/s CMOS limiting amplifier using folded active inductors , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[6]  Yoshiyasu Doi,et al.  A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process , 2013, IEEE Journal of Solid-State Circuits.

[7]  Pervez M. Aziz,et al.  A 1.0625 $\sim$ 14.025 Gb/s Multi-Media Transceiver With Full-Rate Source-Series-Terminated Transmit Driver and Floating-Tap Decision-Feedback Equalizer in 40 nm CMOS , 2011, IEEE Journal of Solid-State Circuits.

[8]  Michael Frueh,et al.  Design Of Integrated Circuits For Optical Communications , 2016 .

[9]  E. Sackinger,et al.  A 3-GHz 32-dB CMOS limiting amplifier for SONET OC-48 receivers , 2000, IEEE Journal of Solid-State Circuits.

[10]  Pervez M. Aziz,et al.  A 1.0625-to-14.025Gb/s multimedia transceiver with full-rate source-series-terminated transmit driver and floating-tap decision-feedback equalizer in 40nm CMOS , 2011, 2011 IEEE International Solid-State Circuits Conference.

[11]  Mounir Meghelli,et al.  A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing drifts in 45-nm SOI CMOS technology , 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

[12]  Rabin Raut,et al.  A low power Transimpedance Amplifier using inductive feedback approach in 90nm CMOS , 2009, 2009 IEEE International Symposium on Circuits and Systems.

[13]  Thomas Toifl,et al.  A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology , 2012, IEEE Journal of Solid-State Circuits.

[14]  Jianwen Zhu,et al.  A 1-Tap 40-Gbps Look-ahead Decision Feedback Equalizer in 0.18μm SiGe BiCMOS Technology , 2005 .

[15]  Thomas Toifl,et al.  A T-Coil-Enhanced 8.5 Gb/s High-Swing SST Transmitter in 65 nm Bulk CMOS With $≪ -$16 dB Return Loss Over 10 GHz Bandwidth , 2008, IEEE Journal of Solid-State Circuits.

[16]  Jeff Sanders,et al.  A 225mW 28Gb/s SerDes in 40nm CMOS with 13dB of analog equalization for 100GBASE-LR4 and optical transport lane 4.4 applications , 2012, 2012 IEEE International Solid-State Circuits Conference.

[17]  Behzad Razavi,et al.  Low-Power CMOS Equalizer Design for 20-Gb/s Systems , 2011, IEEE Journal of Solid-State Circuits.

[18]  E. Alon,et al.  Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery , 2005, IEEE Journal of Solid-State Circuits.

[19]  J.H. Winters,et al.  Techniques for High-Speed Implementation of Nonlinear Cancellation , 1991, IEEE J. Sel. Areas Commun..

[20]  Tao Wang,et al.  3–10-GHz Ultra-Wideband Low-Noise Amplifier Utilizing Miller Effect and Inductive Shunt–Shunt Feedback Technique , 2007, IEEE Transactions on Microwave Theory and Techniques.

[21]  W. Walker,et al.  A 32Gb/s wireline receiver with a low-frequency equalizer, CTLE and 2-tap DFE in 28nm CMOS , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.