Advanced Current Calibration
暂无分享,去创建一个
[1] K. O'Sullivan,et al. A 12-bit 320-MSample/s current-steering CMOS D/A converter in 0.44 mm/sup 2/ , 2004, IEEE Journal of Solid-State Circuits.
[2] Ron Hogervorst,et al. A compact power-efficient 3 V CMOS rail-to-rail input/output operational amplifier for VLSI cell libraries , 1994 .
[3] Kok Lim Chan,et al. A 150MS/s 14-bit Segmented DEM DAC with Greater than 83dB of SFDR Across the Nyquilst band , 2007, 2007 IEEE Symposium on VLSI Circuits.
[4] W. Groeneveld,et al. A self calibration technique for monolithic high-resolution D/A converters , 1989, IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers.
[5] Michiel Steyaert,et al. A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter , 2001 .
[6] Takafumi Yamaji,et al. A 1.2-V, 12-bit, 200M sample/s current-steering D/A converter in 90-nm CMOS , 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..
[7] M. Clara,et al. A 1.5V 13bit 130-300MS/s self-calibrated DAC with active output stage and 50MHz signal bandwidth in 0.13μm CMOS , 2008, ESSCIRC 2008 - 34th European Solid-State Circuits Conference.
[8] Antonio Di Giandomenico,et al. A 1.5V 200MS/s 13b 25mW DAC with Randomized Nested Background Calibration in 0.13/spl mu/m CMOS , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[9] Kenneth R. Laker,et al. Design of analog integrated circuits and systems , 1994 .
[10] Jieh-Tsorng Wu,et al. A 12-Bit 1.25-GS/s DAC in 90 nm CMOS With $ > $70 dB SFDR up to 500 MHz , 2011, IEEE Journal of Solid-State Circuits.
[11] Yu Lin,et al. A 12 bit 2.9 GS/s DAC With IM3 $ ≪ -$60 dBc Beyond 1 GHz in 65 nm CMOS , 2009, IEEE Journal of Solid-State Circuits.
[12] John D. Hyde,et al. A 300-MS/s 14-bit digital-to-analog converter in logic CMOS , 2003, IEEE J. Solid State Circuits.
[13] Michiel Steyaert,et al. Static and Dynamic Performance Limitations for High Speed D/A Converters , 2004 .
[14] Yonghua Cong,et al. A 1.5 V 14 b 100 MS/s self-calibrated DAC , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..
[15] Kok Lim Chan,et al. A 14b 100MS/s DAC with Fully Segmented Dynamic Element Matching , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.
[16] W. Schofield,et al. A 16b 400MS/s DAC with <-80dBc IMD to 300MHz and <-160dBm/Hz noise power spectral density , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..
[17] M. P. Tiilikainen. A 14-bit 1.8-V 20-mW 1-mm/sup 2/ CMOS DAC , 2001 .
[18] K. Bult,et al. A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2 , 1998, IEEE J. Solid State Circuits.
[19] Qiuting Huang,et al. A 200MS/s 14b 97mW DAC in 0.18/spl mu/m CMOS , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).
[20] Robert H. M. van Veldhoven,et al. A 14 bit 200 MS/s DAC With SFDR >78 dBc, IM3 < -83 dBc and NSD <-163 dBm/Hz Across the Whole Nyquist Band Enabled by Dynamic-Mismatch Mapping , 2011, IEEE Journal of Solid-State Circuits.
[21] D. Monticelli. A quad CMOS single-supply op amp with rail-to-rail output swing , 1986 .
[22] H. Weinrichter,et al. Stochastische Grundlagen nachrichtentechnischer Signale , 1991 .
[23] M.S.J. Steyaert,et al. A 10-bit 250-MS/s binary-weighted current-steering DAC , 2004, IEEE Journal of Solid-State Circuits.
[24] Bang-Sup Song,et al. A self-trimming 14-b 100-MS/s CMOS DAC , 2000, IEEE Journal of Solid-State Circuits.
[25] M. Steyaert,et al. A 12 b 500 MSample/s current-steering CMOS D/A converter , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).