High-speed MRAM for Embedding in SoC

Introduction (Positioning of memories): Magnetoresistive random access memories (MRAMs) have unique attributes that are not found in any other nonvolatile memories, such as non-volatility, high-speed operation, unlimited read-write endurance and hightemperature operation. Therefore, they have great potential as non-volatile working memories, which replace volatile working memories such as SRAMs and DRAMs. The positioning of conventional memory technologies is shown in Fig. 1. The horizontal axis represents the cell area factor, corresponding to chip cost, and the vertical axis represents the operating frequency, corresponding to performance. There is a tradeoff between chip cost and performance. Flash has the smallest cells, which are suitable for large-capacity storage, but its operating speed is low. SRAMs, on the other hand, which require high-speed data transmission to logic circuits, have relatively large cells. First-generation MRAMs, which have already been commercialized, are positioned in the middle of these memory technologies and are placed slightly lower than DRAMs and SRAMs, as shown in Fig. 1. This positioning limits the expansion of MRAM applications and markets, so both higher-speed embedding and larger capacities are essential targets for next generation MRAMs. This paper describes new MRAM-cell technology that is suitable for high-speed memory macros embedded in SoCs. MRAM cell for embedded applications: MTJ polarization in first-generation MRAM writing schemes is switched by a synthesized magnetic field induced by two writing currents through the word line and bit line. These currents must be precisely controlled so that they are within the lower and upper limits to avoid multiple writing in half-selected cells. This complicates the write-current source. As a result, achieving write operation over 100 MHz is difficult because the writingcurrent duration is around 10 ns. To address this problem, we developed a new MRAMcell suitable for high-speed memory macros embedded in SoCs. The cell consists of two pass transistors (M1 and M2) and one MTJ overlying a write line connected to both transistors. This two-transistor single-MTJ (2T1MTJ) cell greatly improves cell selectivity and eliminates both the upper limit of the write current and the requirement of accurate current control. This simplifies the write circuit, thus it can easily be composed of logic gates, like an SRAM’s decoder. Because this simplified write circuit can easily change the direction of the writing current by supplying complementary voltage to the BL and BLb in accordance with the input data, the circuit can supply a writing current waveform of less than 1 ns. A 250-MHz 1-Mbit MRAM macro has been demonstrated in a 0.15-μm standard CMOS process with 1.5-V supply by using a 2T1MTJ cell. Its clock frequency is the highest among the MRAMs that have been reported, and it has a highly compatible embedded-SRAM interface. MTJ polarization in 2T1MTJ cells is switched by a magnetic field using the one write line current that flows through the write line in a selected cell. The MTJ is placed directly on the write line to effectively enhance the magnetic field. Because the cell area should be as small as possible, reducing the current to under 1 mA so that the cell area is less than or equal to the SRAM cell area is necessary. We developed a new MTJ element with an inserted write line. It has two free layers with a low aspect ratio, and the write line has been directly inserted between the layers. These free layers are magnetostatically coupled to each other, which provides good switching properties even with a low aspect ratio. Therefore, the switching current is much smaller than that of conventional MTJs. Current-induced magnetic domain wall motion (DWM), on the other hand, is an attractive phenomenon for the development of scalable magnetic memories. We created a new memory cell using DWM (Fig. 2). The cell has two ends that fix magnetization as spin injectors and a middle part that moves a DW. A single DW was introduced and trapped in the end of the middle part and was moved by spin-polarized electrons. The DW positions corresponded to the stored data. Placing an MTJ in the DW-moving region made it possible to detect the direction of magnetization. As the cell size is reduced, the writing current and write time decreases. We expect the DW cell to be used as a scalable memory cell. Conclusion: MRAMs have unique attributes that are not found in any other memory technologies, such as non-volatility, high-speed operation, unlimited read-write endurance, and high-temperature operation. With these characteristics, they have great potential as working memories. When sufficient progress has been made towards this goal, MRAMs will have many fields of application for replacing the conventional volatile macros used in system LSIs. Acknowledgments: A portion of this work was supported by the New Energy and Industrial Technology Development Organization (NEDO). References: 1) N.Sakimura et al., IEEE J. Solid-State Circuits 42, p.830, 2007. 2) N.Sakimura et al., ASSCC Proceedings of Technical Papers, p. 216, 2007. 3) A.Yamaguchi et al., Phys. Rev. Lett. 92, p. 077205, 2004. 4) M.Yamanouchi et al., NATURE, 428, p.539, 1 April 2004. 5) H.Numata et al., 2007 VLSI Tech. Dig. p. 232, 2007.