Verification of Memory Management Units

This paper describes the formal verification of two memory management units using the HOL theorem prover. The verification effort demonstrates the use of hierarchical decomposition and abstract theories. Both devices authorize memory requests and translate virtual addresses to real addresses. The first unit was designed and verified to the gate level. The second memory management unit is implemented with an abstract representation and provides some operating system support. Memory requests are validated based on a memory resident segment table. These units are being used as a basis for the verification of a composed chip set to form a trusted computing base.

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