Variation aware placement for FPGAs

Impact of variations in different process parameters like, gate length, threshold voltage, oxide thickness etc. have been discussed in different components of digital circuits extensively in recent times. The various manufacturing effects on different process parameters have been demonstrated in Borkar et al., 2004 and Nassif, 2001. Degradation in the operating frequencies by nearly 2times and increase in leakage power consumption by a factor of 3, have been demonstrated in FPGAs in Yan et al., 2005. In this paper, we propose a variation aware placement scheme in FPGAs and demonstrate the effectiveness of the scheme on Xilinx FPGAs and regular island style FPGAs. Our approach provides leakage benefits close to 14% on an average over different benchmark designs