Multi-patterning lithography at the 10-nm and 7-nm nodes is driving the allowed overlay error down to extreme low values. Advanced high order overlay correction schemes are needed to control the process variability. Additionally the increase of the number of split layers results in an exponential increase of metrology complexity of the total overlay and alignment tree. At the same time, the process stack includes more hard-mask steps and becomes more and more complex, with as consequence that the setup and verification of the overlay metrology recipe becomes more critical. All of the above require a holistic approach that addresses total overlay optimization from process design to process setup and control in volume manufacturing. In this paper we will present the holistic overlay control flow designed for 10-nm and 7-nm nodes and illustrate the achievable ultimate overlay performance for a logic and DRAM use case. As figure 1 illustrates we will explain the details of the steps in the holistic flow. Overlay accuracy is the driver for target design and metrology tool optimization like wavelength and polarization. We will show that it is essential to include processing effects like etching and CMP which can result in a physical asymmetry of the bottom grating of diffraction based overlay targets. We will introduce a new method to create a reference overlay map, based on metrology data using multiple wavelengths and polarization settings. A similar approach is developed for the wafer alignment step. The overlay fingerprint correction using linear or high order correction per exposure (CPE) has a large amount of parameters. It is critical to balance the metrology noise with the ultimate correction model and the related metrology sampling scheme. Similar approach is needed for the wafer align step. Both for overlay control as well as alignment we have developed methods which include efficient use of metrology time, available for an in the litho-cluster integrated metrology use. These methods include a novel set models that efficiently describe different process fingerprints. We will explain the methods and show the benefits for logic and DRAM use cases.